📄 signal_gene.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "inclock register address\[5\] register address\[0\] 45.05 MHz 22.2 ns Internal " "Info: Clock \"inclock\" has Internal fmax of 45.05 MHz between source register \"address\[5\]\" and destination register \"address\[0\]\" (period= 22.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "21.100 ns + Longest register register " "Info: + Longest register to register delay is 21.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns address\[5\] 1 REG LC1_B29 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B29; Fanout = 15; REG Node = 'address\[5\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { address[5] } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.600 ns) 2.700 ns LessThan1~394 2 COMB LC3_B33 2 " "Info: 2: + IC(1.100 ns) + CELL(1.600 ns) = 2.700 ns; Loc. = LC3_B33; Fanout = 2; COMB Node = 'LessThan1~394'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { address[5] LessThan1~394 } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.100 ns) 4.100 ns LessThan1~415 3 COMB LC5_B33 1 " "Info: 3: + IC(0.300 ns) + CELL(1.100 ns) = 4.100 ns; Loc. = LC5_B33; Fanout = 1; COMB Node = 'LessThan1~415'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { LessThan1~394 LessThan1~415 } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 5.100 ns LessThan1~417 4 COMB LC6_B33 1 " "Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 5.100 ns; Loc. = LC6_B33; Fanout = 1; COMB Node = 'LessThan1~417'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.000 ns" { LessThan1~415 LessThan1~417 } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 6.700 ns LessThan1~403 5 COMB LC7_B33 2 " "Info: 5: + IC(0.000 ns) + CELL(1.600 ns) = 6.700 ns; Loc. = LC7_B33; Fanout = 2; COMB Node = 'LessThan1~403'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { LessThan1~417 LessThan1~403 } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.700 ns) 9.400 ns address~1927 6 COMB LC4_B32 2 " "Info: 6: + IC(1.000 ns) + CELL(1.700 ns) = 9.400 ns; Loc. = LC4_B32; Fanout = 2; COMB Node = 'address~1927'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { LessThan1~403 address~1927 } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 11.100 ns address~1932 7 COMB LC8_B32 1 " "Info: 7: + IC(0.300 ns) + CELL(1.400 ns) = 11.100 ns; Loc. = LC8_B32; Fanout = 1; COMB Node = 'address~1932'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { address~1927 address~1932 } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 12.800 ns address~1934 8 COMB LC1_B32 9 " "Info: 8: + IC(0.300 ns) + CELL(1.400 ns) = 12.800 ns; Loc. = LC1_B32; Fanout = 9; COMB Node = 'address~1934'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { address~1932 address~1934 } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.400 ns) 15.200 ns address~1977 9 COMB LC1_B35 1 " "Info: 9: + IC(1.000 ns) + CELL(1.400 ns) = 15.200 ns; Loc. = LC1_B35; Fanout = 1; COMB Node = 'address~1977'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { address~1934 address~1977 } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 17.800 ns Mux8~4 10 COMB LC3_B34 1 " "Info: 10: + IC(1.000 ns) + CELL(1.600 ns) = 17.800 ns; Loc. = LC3_B34; Fanout = 1; COMB Node = 'Mux8~4'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.600 ns" { address~1977 Mux8~4 } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 19.700 ns Mux8~5 11 COMB LC4_B34 1 " "Info: 11: + IC(0.300 ns) + CELL(1.600 ns) = 19.700 ns; Loc. = LC4_B34; Fanout = 1; COMB Node = 'Mux8~5'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { Mux8~4 Mux8~5 } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.100 ns) 21.100 ns address\[0\] 12 REG LC5_B34 17 " "Info: 12: + IC(0.300 ns) + CELL(1.100 ns) = 21.100 ns; Loc. = LC5_B34; Fanout = 17; REG Node = 'address\[0\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { Mux8~5 address[0] } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "15.500 ns ( 73.46 % ) " "Info: Total cell delay = 15.500 ns ( 73.46 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.600 ns ( 26.54 % ) " "Info: Total interconnect delay = 5.600 ns ( 26.54 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "21.100 ns" { address[5] LessThan1~394 LessThan1~415 LessThan1~417 LessThan1~403 address~1927 address~1932 address~1934 address~1977 Mux8~4 Mux8~5 address[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "21.100 ns" { address[5] LessThan1~394 LessThan1~415 LessThan1~417 LessThan1~403 address~1927 address~1932 address~1934 address~1977 Mux8~4 Mux8~5 address[0] } { 0.000ns 1.100ns 0.300ns 0.000ns 0.000ns 1.000ns 0.300ns 0.300ns 1.000ns 1.000ns 0.300ns 0.300ns } { 0.000ns 1.600ns 1.100ns 1.000ns 1.600ns 1.700ns 1.400ns 1.400ns 1.400ns 1.600ns 1.600ns 1.100ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclock destination 2.400 ns + Shortest register " "Info: + Shortest clock path from clock \"inclock\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns inclock 1 CLK PIN_54 96 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 96; CLK Node = 'inclock'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclock } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns address\[0\] 2 REG LC5_B34 17 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC5_B34; Fanout = 17; REG Node = 'address\[0\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { inclock address[0] } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { inclock address[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { inclock inclock~out address[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclock source 2.400 ns - Longest register " "Info: - Longest clock path from clock \"inclock\" to source register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns inclock 1 CLK PIN_54 96 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 96; CLK Node = 'inclock'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclock } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns address\[5\] 2 REG LC1_B29 15 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC1_B29; Fanout = 15; REG Node = 'address\[5\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { inclock address[5] } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { inclock address[5] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { inclock inclock~out address[5] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { inclock address[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { inclock inclock~out address[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { inclock address[5] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { inclock inclock~out address[5] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" { } { { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 10 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 10 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "21.100 ns" { address[5] LessThan1~394 LessThan1~415 LessThan1~417 LessThan1~403 address~1927 address~1932 address~1934 address~1977 Mux8~4 Mux8~5 address[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "21.100 ns" { address[5] LessThan1~394 LessThan1~415 LessThan1~417 LessThan1~403 address~1927 address~1932 address~1934 address~1977 Mux8~4 Mux8~5 address[0] } { 0.000ns 1.100ns 0.300ns 0.000ns 0.000ns 1.000ns 0.300ns 0.300ns 1.000ns 1.000ns 0.300ns 0.300ns } { 0.000ns 1.600ns 1.100ns 1.000ns 1.600ns 1.700ns 1.400ns 1.400ns 1.400ns 1.600ns 1.600ns 1.100ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { inclock address[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { inclock inclock~out address[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { inclock address[5] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { inclock inclock~out address[5] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "k\[0\] i\[0\] inclock 41.800 ns register " "Info: tsu for register \"k\[0\]\" (data pin = \"i\[0\]\", clock pin = \"inclock\") is 41.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "43.600 ns + Longest pin register " "Info: + Longest pin to register delay is 43.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns i\[0\] 1 PIN PIN_8 15 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_8; Fanout = 15; PIN Node = 'i\[0\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { i[0] } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.400 ns) + CELL(1.600 ns) 10.900 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|StageOut\[5\] 2 COMB LC7_F18 3 " "Info: 2: + IC(4.400 ns) + CELL(1.600 ns) = 10.900 ns; Loc. = LC7_F18; Fanout = 3; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|StageOut\[5\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { i[0] lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[5] } "NODE_NAME" } } { "db/alt_u_div_gie.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/alt_u_div_gie.tdf" 60 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.700 ns) 13.200 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_l7c:add_sub_2\|add_sub_cella\[1\]~COUT 3 COMB LC2_F4 2 " "Info: 3: + IC(1.600 ns) + CELL(0.700 ns) = 13.200 ns; Loc. = LC2_F4; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_l7c:add_sub_2\|add_sub_cella\[1\]~COUT'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[5] lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|add_sub_cella[1]~COUT } "NODE_NAME" } } { "db/add_sub_l7c.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/add_sub_l7c.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 13.400 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_l7c:add_sub_2\|cout 4 COMB LC3_F4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 13.400 ns; Loc. = LC3_F4; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_l7c:add_sub_2\|cout'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|add_sub_cella[1]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|cout } "NODE_NAME" } } { "db/add_sub_l7c.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/add_sub_l7c.tdf" 39 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 14.800 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_l7c:add_sub_2\|add_sub_cella\[2\]~76 5 COMB LC4_F4 6 " "Info: 5: + IC(0.000 ns) + CELL(1.400 ns) = 14.800 ns; Loc. = LC4_F4; Fanout = 6; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_l7c:add_sub_2\|add_sub_cella\[2\]~76'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|cout lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|add_sub_cella[2]~76 } "NODE_NAME" } } { "db/add_sub_l7c.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/add_sub_l7c.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.600 ns) 18.900 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_m7c:add_sub_3\|_~14 6 COMB LC7_B14 1 " "Info: 6: + IC(2.500 ns) + CELL(1.600 ns) = 18.900 ns; Loc. = LC7_B14; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_m7c:add_sub_3\|_~14'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.100 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|add_sub_cella[2]~76 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_m7c:add_sub_3|_~14 } "NODE_NAME" } } { "db/alt_u_div_gie.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/alt_u_div_gie.tdf" 44 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.700 ns) 22.900 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[1\] 7 COMB LC4_F14 1 " "Info: 7: + IC(2.300 ns) + CELL(1.700 ns) = 22.900 ns; Loc. = LC4_F14; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_m7c:add_sub_3\|add_sub_cella\[1\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_m7c:add_sub_3|_~14 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_m7c:add_sub_3|add_sub_cella[1] } "NODE_NAME" } } { "db/add_sub_m7c.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/add_sub_m7c.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(1.400 ns) 25.800 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|StageOut\[16\]~735 8 COMB LC3_F17 4 " "Info: 8: + IC(1.500 ns) + CELL(1.400 ns) = 25.800 ns; Loc. = LC3_F17; Fanout = 4; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|StageOut\[16\]~735'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_m7c:add_sub_3|add_sub_cella[1] lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[16]~735 } "NODE_NAME" } } { "db/alt_u_div_gie.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/alt_u_div_gie.tdf" 60 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.700 ns) 27.900 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[2\]~COUT 9 COMB LC1_F16 2 " "Info: 9: + IC(1.400 ns) + CELL(0.700 ns) = 27.900 ns; Loc. = LC1_F16; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[2\]~COUT'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[16]~735 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[2]~COUT } "NODE_NAME" } } { "db/add_sub_n7c.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/add_sub_n7c.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 28.100 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[3\]~COUT 10 COMB LC2_F16 1 " "Info: 10: + IC(0.000 ns) + CELL(0.200 ns) = 28.100 ns; Loc. = LC2_F16; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[3\]~COUT'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[2]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[3]~COUT } "NODE_NAME" } } { "db/add_sub_n7c.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/add_sub_n7c.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 28.300 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_4\|cout 11 COMB LC3_F16 2 " "Info: 11: + IC(0.000 ns) + CELL(0.200 ns) = 28.300 ns; Loc. = LC3_F16; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_4\|cout'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[3]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|cout } "NODE_NAME" } } { "db/add_sub_n7c.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/add_sub_n7c.tdf" 39 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 29.700 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[4\]~371 12 COMB LC4_F16 7 " "Info: 12: + IC(0.000 ns) + CELL(1.400 ns) = 29.700 ns; Loc. = LC4_F16; Fanout = 7; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_4\|add_sub_cella\[4\]~371'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|cout lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[4]~371 } "NODE_NAME" } } { "db/add_sub_n7c.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/add_sub_n7c.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(1.600 ns) 32.800 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|StageOut\[21\]~742 13 COMB LC7_F17 3 " "Info: 13: + IC(1.500 ns) + CELL(1.600 ns) = 32.800 ns; Loc. = LC7_F17; Fanout = 3; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|StageOut\[21\]~742'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[4]~371 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[21]~742 } "NODE_NAME" } } { "db/alt_u_div_gie.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/alt_u_div_gie.tdf" 60 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.700 ns) 34.900 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_5\|add_sub_cella\[2\]~COUT 14 COMB LC6_F16 2 " "Info: 14: + IC(1.400 ns) + CELL(0.700 ns) = 34.900 ns; Loc. = LC6_F16; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_5\|add_sub_cella\[2\]~COUT'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[21]~742 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[2]~COUT } "NODE_NAME" } } { "db/add_sub_n7c.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/add_sub_n7c.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 35.100 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_5\|add_sub_cella\[3\]~COUT 15 COMB LC7_F16 1 " "Info: 15: + IC(0.000 ns) + CELL(0.200 ns) = 35.100 ns; Loc. = LC7_F16; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_5\|add_sub_cella\[3\]~COUT'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[2]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[3]~COUT } "NODE_NAME" } } { "db/add_sub_n7c.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/add_sub_n7c.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 35.300 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_5\|cout 16 COMB LC8_F16 2 " "Info: 16: + IC(0.000 ns) + CELL(0.200 ns) = 35.300 ns; Loc. = LC8_F16; Fanout = 2; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_5\|cout'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[3]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|cout } "NODE_NAME" } } { "db/add_sub_n7c.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/add_sub_n7c.tdf" 39 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(1.400 ns) 37.200 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_5\|add_sub_cella\[4\]~389 17 COMB LC1_F18 5 " "Info: 17: + IC(0.500 ns) + CELL(1.400 ns) = 37.200 ns; Loc. = LC1_F18; Fanout = 5; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_5\|add_sub_cella\[4\]~389'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|cout lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[4]~389 } "NODE_NAME" } } { "db/add_sub_n7c.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/add_sub_n7c.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.600 ns) 40.200 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|StageOut\[26\]~744 18 COMB LC5_F17 1 " "Info: 18: + IC(1.400 ns) + CELL(1.600 ns) = 40.200 ns; Loc. = LC5_F17; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|StageOut\[26\]~744'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[4]~389 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[26]~744 } "NODE_NAME" } } { "db/alt_u_div_gie.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/alt_u_div_gie.tdf" 60 10 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(0.700 ns) 42.400 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_6\|add_sub_cella\[2\]~COUT 19 COMB LC3_F18 1 " "Info: 19: + IC(1.500 ns) + CELL(0.700 ns) = 42.400 ns; Loc. = LC3_F18; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_6\|add_sub_cella\[2\]~COUT'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[26]~744 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|add_sub_cella[2]~COUT } "NODE_NAME" } } { "db/add_sub_n7c.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/add_sub_n7c.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 42.600 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_6\|add_sub_cella\[3\]~COUT 20 COMB LC4_F18 1 " "Info: 20: + IC(0.000 ns) + CELL(0.200 ns) = 42.600 ns; Loc. = LC4_F18; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_6\|add_sub_cella\[3\]~COUT'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|add_sub_cella[2]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|add_sub_cella[3]~COUT } "NODE_NAME" } } { "db/add_sub_n7c.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/add_sub_n7c.tdf" 32 15 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 42.800 ns lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_6\|cout 21 COMB LC5_F18 1 " "Info: 21: + IC(0.000 ns) + CELL(0.200 ns) = 42.800 ns; Loc. = LC5_F18; Fanout = 1; COMB Node = 'lpm_divide:Div0\|lpm_divide_qvl:auto_generated\|sign_div_unsign_6kh:divider\|alt_u_div_gie:divider\|add_sub_n7c:add_sub_6\|cout'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|add_sub_cella[3]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|cout } "NODE_NAME" } } { "db/add_sub_n7c.tdf" "" { Text "d:/我的文档/桌面/signal_gene/db/add_sub_n7c.tdf" 39 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 43.600 ns k\[0\] 22 REG LC6_F18 5 " "Info: 22: + IC(0.000 ns) + CELL(0.800 ns) = 43.600 ns; Loc. = LC6_F18; Fanout = 5; REG Node = 'k\[0\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.800 ns" { lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|cout k[0] } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "23.600 ns ( 54.13 % ) " "Info: Total cell delay = 23.600 ns ( 54.13 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "20.000 ns ( 45.87 % ) " "Info: Total interconnect delay = 20.000 ns ( 45.87 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "43.600 ns" { i[0] lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[5] lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|add_sub_cella[1]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|cout lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|add_sub_cella[2]~76 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_m7c:add_sub_3|_~14 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_m7c:add_sub_3|add_sub_cella[1] lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[16]~735 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[2]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[3]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|cout lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[4]~371 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[21]~742 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[2]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[3]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|cout lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[4]~389 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[26]~744 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|add_sub_cella[2]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|add_sub_cella[3]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|cout k[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "43.600 ns" { i[0] i[0]~out lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[5] lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|add_sub_cella[1]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|cout lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|add_sub_cella[2]~76 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_m7c:add_sub_3|_~14 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_m7c:add_sub_3|add_sub_cella[1] lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[16]~735 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[2]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[3]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|cout lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[4]~371 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[21]~742 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[2]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[3]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|cout lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[4]~389 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[26]~744 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|add_sub_cella[2]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|add_sub_cella[3]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|cout k[0] } { 0.000ns 0.000ns 4.400ns 1.600ns 0.000ns 0.000ns 2.500ns 2.300ns 1.500ns 1.400ns 0.000ns 0.000ns 0.000ns 1.500ns 1.400ns 0.000ns 0.000ns 0.500ns 1.400ns 1.500ns 0.000ns 0.000ns 0.000ns } { 0.000ns 4.900ns 1.600ns 0.700ns 0.200ns 1.400ns 1.600ns 1.700ns 1.400ns 0.700ns 0.200ns 0.200ns 1.400ns 1.600ns 0.700ns 0.200ns 0.200ns 1.400ns 1.600ns 0.700ns 0.200ns 0.200ns 0.800ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 10 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclock destination 2.400 ns - Shortest register " "Info: - Shortest clock path from clock \"inclock\" to destination register is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns inclock 1 CLK PIN_54 96 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 96; CLK Node = 'inclock'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclock } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.000 ns) 2.400 ns k\[0\] 2 REG LC6_F18 5 " "Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_F18; Fanout = 5; REG Node = 'k\[0\]'" { } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { inclock k[0] } "NODE_NAME" } } { "signal_gene.v" "" { Text "d:/我的文档/桌面/signal_gene/signal_gene.v" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 83.33 % ) " "Info: Total cell delay = 2.000 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.400 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.400 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { inclock k[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { inclock inclock~out k[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "43.600 ns" { i[0] lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[5] lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|add_sub_cella[1]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|cout lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|add_sub_cella[2]~76 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_m7c:add_sub_3|_~14 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_m7c:add_sub_3|add_sub_cella[1] lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[16]~735 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[2]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[3]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|cout lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[4]~371 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[21]~742 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[2]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[3]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|cout lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[4]~389 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[26]~744 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|add_sub_cella[2]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|add_sub_cella[3]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|cout k[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "43.600 ns" { i[0] i[0]~out lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[5] lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|add_sub_cella[1]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|cout lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_l7c:add_sub_2|add_sub_cella[2]~76 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_m7c:add_sub_3|_~14 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_m7c:add_sub_3|add_sub_cella[1] lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[16]~735 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[2]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[3]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|cout lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_4|add_sub_cella[4]~371 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[21]~742 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[2]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[3]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|cout lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_5|add_sub_cella[4]~389 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|StageOut[26]~744 lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|add_sub_cella[2]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|add_sub_cella[3]~COUT lpm_divide:Div0|lpm_divide_qvl:auto_generated|sign_div_unsign_6kh:divider|alt_u_div_gie:divider|add_sub_n7c:add_sub_6|cout k[0] } { 0.000ns 0.000ns 4.400ns 1.600ns 0.000ns 0.000ns 2.500ns 2.300ns 1.500ns 1.400ns 0.000ns 0.000ns 0.000ns 1.500ns 1.400ns 0.000ns 0.000ns 0.500ns 1.400ns 1.500ns 0.000ns 0.000ns 0.000ns } { 0.000ns 4.900ns 1.600ns 0.700ns 0.200ns 1.400ns 1.600ns 1.700ns 1.400ns 0.700ns 0.200ns 0.200ns 1.400ns 1.600ns 0.700ns 0.200ns 0.200ns 1.400ns 1.600ns 0.700ns 0.200ns 0.200ns 0.800ns } "" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { inclock k[0] } "NODE_NAME" } } { "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.400 ns" { inclock inclock~out k[0] } { 0.000ns 0.000ns 0.400ns } { 0.000ns 2.000ns 0.000ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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