signal_gene.hif

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Version 7.0 Build 33 02/05/2007 SJ Full Version
2
24
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
datarom
# storage
db|signal_gene.(1).cnf
db|signal_gene.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
datarom.v
b4316aa2292aa9e8776359d96fceefc
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
datarom:datarom_component
}
# end
# entity
signal_gene
# storage
db|signal_gene.(0).cnf
db|signal_gene.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
signal_gene.v
d87c5949c47bd9ce56fcb6b4fb5d313
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
|
}
# end
# entity
mult_0f01
# storage
db|signal_gene.(13).cnf
db|signal_gene.(13).cnf
# case_insensitive
# source_file
db|mult_0f01.tdf
8e909c6b1c727748e3dc6ced9fbe13d
6
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
}
# end
# entity
lpm_divide_qvl
# storage
db|signal_gene.(15).cnf
db|signal_gene.(15).cnf
# case_insensitive
# source_file
db|lpm_divide_qvl.tdf
65633ddd95b4b9c9c7bec1a93401054
6
# used_port {
quotient6
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numer6
-1
3
numer5
-1
3
numer4
-1
3
numer3
-1
3
numer2
-1
3
numer1
-1
3
numer0
-1
3
denom3
-1
3
denom2
-1
3
denom1
-1
3
denom0
-1
3
}
# end
# entity
sign_div_unsign_6kh
# storage
db|signal_gene.(16).cnf
db|signal_gene.(16).cnf
# case_insensitive
# source_file
db|sign_div_unsign_6kh.tdf
8380194a63a6968491734ad8979742c9
6
# used_port {
remainder3
-1
3
remainder2
-1
3
remainder1
-1
3
remainder0
-1
3
quotient6
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numerator6
-1
3
numerator5
-1
3
numerator4
-1
3
numerator3
-1
3
numerator2
-1
3
numerator1
-1
3
numerator0
-1
3
denominator3
-1
3
denominator2
-1
3
denominator1
-1
3
denominator0
-1
3
}
# end
# entity
alt_u_div_gie
# storage
db|signal_gene.(17).cnf
db|signal_gene.(17).cnf
# case_insensitive
# source_file
db|alt_u_div_gie.tdf
628f945cf97cdfadaa26175d5ef946b
6
# used_port {
remainder3
-1
3
remainder2
-1
3
remainder1
-1
3
remainder0
-1
3
quotient6
-1
3
quotient5
-1
3
quotient4
-1
3
quotient3
-1
3
quotient2
-1
3
quotient1
-1
3
quotient0
-1
3
numerator6
-1
3
numerator5
-1
3
numerator4
-1
3
numerator3
-1
3
numerator2
-1
3
numerator1
-1
3
numerator0
-1
3
denominator3
-1
3
denominator2
-1
3
denominator1
-1
3
denominator0
-1
3
}
# end
# entity
add_sub_j7c
# storage
db|signal_gene.(18).cnf
db|signal_gene.(18).cnf
# case_insensitive
# source_file
db|add_sub_j7c.tdf
fac152dcad5491642f95e7e9dbce35
6
# used_port {
result0
-1
3
datab0
-1
3
dataa0
-1
3
cout
-1
3
}
# end
# entity
add_sub_k7c
# storage
db|signal_gene.(19).cnf
db|signal_gene.(19).cnf
# case_insensitive
# source_file
db|add_sub_k7c.tdf
76fb35e884d8a5692e488e9feb14c33
6
# used_port {
result1
-1
3
result0
-1
3
datab1
-1
3
datab0
-1
3
dataa1
-1
3
dataa0
-1
3
cout
-1
3
}
# end
# entity
add_sub_l7c
# storage
db|signal_gene.(20).cnf
db|signal_gene.(20).cnf
# case_insensitive
# source_file
db|add_sub_l7c.tdf
6ea48d9ef783c99cdb1268990c372
6
# used_port {
result2
-1
3
result1
-1
3
result0
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
cout
-1
3
}
# end
# entity
add_sub_m7c
# storage
db|signal_gene.(21).cnf
db|signal_gene.(21).cnf
# case_insensitive
# source_file
db|add_sub_m7c.tdf
1b3c544f29b0767a721b085b016f6f4
6
# used_port {
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
cout
-1
3
}
# end
# entity
add_sub_n7c
# storage
db|signal_gene.(22).cnf
db|signal_gene.(22).cnf
# case_insensitive
# source_file
db|add_sub_n7c.tdf
856f9ec4f9a0cc352e9173cfb75dec2a
6
# used_port {
result4
-1
3
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
cout
-1
3
}
# end
# entity
add_sub_l3c
# storage
db|signal_gene.(23).cnf
db|signal_gene.(23).cnf
# case_insensitive
# source_file
db|add_sub_l3c.tdf
8a11717eeb1234a3a8632d7499573057
6
# used_port {
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
cin
-1
3
}
# end
# entity
lpm_rom
# storage
db|signal_gene.(2).cnf
db|signal_gene.(2).cnf
# case_insensitive
# source_file
e:|altera|70|quartus|libraries|megafunctions|lpm_rom.tdf
28f29ddc4520aa76d718b6a88061d9e6
6
# user_parameter {
LPM_WIDTH
8
PARAMETER_SIGNED_DEC
USR
LPM_WIDTHAD
9
PARAMETER_SIGNED_DEC
USR
LPM_NUMWORDS
512
PARAMETER_UNKNOWN
DEF
LPM_ADDRESS_CONTROL
REGISTERED
PARAMETER_UNKNOWN
USR
LPM_OUTDATA
UNREGISTERED
PARAMETER_UNKNOWN
USR
LPM_FILE
signal_gene.mif
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
ACEX1K
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
q
-1
3
inclock
-1
3
address
-1
3
outclock
-1
2
memenab
-1
2
}
# include_file {
e:|altera|70|quartus|libraries|megafunctions|aglobal70.inc
6e323611d63cddcc66b682e7ab39d4b7
e:|altera|70|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
}
# hierarchies {
datarom:datarom_component|lpm_rom:lpm_rom_component
}
# end
# entity
altrom
# storage
db|signal_gene.(3).cnf
db|signal_gene.(3).cnf
# case_insensitive
# source_file
e:|altera|70|quartus|libraries|megafunctions|altrom.tdf
d6ecb44ef8345096ad4c1d67d3ece011
6
# user_parameter {
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
WIDTH
8
PARAMETER_UNKNOWN
USR
AD_WIDTH
9
PARAMETER_UNKNOWN
USR
NUMWORDS
512
PARAMETER_UNKNOWN
USR
FILE
signal_gene.mif
PARAMETER_UNKNOWN
USR
REGISTERINPUTMODE
ADDRESS_CONTROL
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
2048
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
ACEX1K
PARAMETER_UNKNOWN
USR
SUPPRESS_MEMORY_CONVERSION_WARNINGS
OFF
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clocki
-1
3
address8
-1
3
address7
-1
3
address6
-1
3
address5
-1
3
address4
-1
3
address3
-1
3
address2
-1
3
address1
-1
3
address0
-1
3
}
# include_file {
e:|altera|70|quartus|libraries|megafunctions|aglobal70.inc
6e323611d63cddcc66b682e7ab39d4b7
e:|altera|70|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
e:|altera|70|quartus|libraries|others|maxplus2|memmodes.inc
44d4551a35f349f0dbacaf799d39950
e:|altera|70|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
e:|altera|70|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
e:|altera|70|quartus|libraries|megafunctions|altsyncram.inc
fcd2728179d3106e487da887737a8940
}
# memory_file {
signal_gene.mif
739f251820a82424aceca9a392fd560
}
# hierarchies {
datarom:datarom_component|lpm_rom:lpm_rom_component|altrom:srom
}
# end
# entity
lpm_add_sub
# storage
db|signal_gene.(4).cnf
db|signal_gene.(4).cnf
# case_insensitive
# source_file
e:|altera|70|quartus|libraries|megafunctions|lpm_add_sub.tdf
b4daf574d78159ba1dbd3e0f8ab3d5e
6
# user_parameter {
LPM_WIDTH
9
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
YES
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
1
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
ACEX1K
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_plh
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
datab8
-1
1
datab7
-1
1
datab6
-1
1