signal_gene.sim.rpt

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; Simulation results format                                                                  ; CVWF       ;               ;
; Add pins automatically to simulation output waveforms                                      ; On         ; On            ;
; Check outputs                                                                              ; Off        ; Off           ;
; Report simulation coverage                                                                 ; On         ; On            ;
; Display complete 1/0 value coverage report                                                 ; On         ; On            ;
; Display missing 1-value coverage report                                                    ; On         ; On            ;
; Display missing 0-value coverage report                                                    ; On         ; On            ;
; Detect setup and hold time violations                                                      ; Off        ; Off           ;
; Detect glitches                                                                            ; On         ; Off           ;
; Glitch interval                                                                            ; 1 ns       ; 1 ns          ;
; Disable timing delays in Timing Simulation                                                 ; Off        ; Off           ;
; Generate Signal Activity File                                                              ; Off        ; Off           ;
; Generate VCD File for PowerPlay Power Analyzer                                             ; Off        ; Off           ;
; Group bus channels in simulation results                                                   ; Off        ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On         ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; Off        ;               ;
; Glitch Filtering                                                                           ; Off        ; Off           ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------------------------+
; |signal_gene|datarom:datarom_component|lpm_rom:lpm_rom_component|altrom:srom|content ;
+--------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      19.54 % ;
; Total nodes checked                                 ; 215          ;
; Total output ports checked                          ; 261          ;
; Total output ports with complete 1/0-value coverage ; 51           ;
; Total output ports with no 1/0-value coverage       ; 188          ;
; Total output ports with no 1-value coverage         ; 193          ;
; Total output ports with no 0-value coverage         ; 205          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                       ;
+--------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+------------------+
; Node Name                                                                                  ; Output Port Name                                                                  ; Output Port Type ;
+--------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+------------------+
; |signal_gene|datarom:datarom_component|lpm_rom:lpm_rom_component|altrom:srom|segment[0][1] ; |signal_gene|datarom:datarom_component|lpm_rom:lpm_rom_component|altrom:srom|q[1] ; dataout          ;
; |signal_gene|datarom:datarom_component|lpm_rom:lpm_rom_component|altrom:srom|segment[0][2] ; |signal_gene|datarom:datarom_component|lpm_rom:lpm_rom_component|altrom:srom|q[2] ; dataout          ;
; |signal_gene|datarom:datarom_component|lpm_rom:lpm_rom_component|altrom:srom|segment[0][3] ; |signal_gene|datarom:datarom_component|lpm_rom:lpm_rom_component|altrom:srom|q[3] ; dataout          ;
; |signal_gene|datarom:datarom_component|lpm_rom:lpm_rom_component|altrom:srom|segment[0][4] ; |signal_gene|datarom:datarom_component|lpm_rom:lpm_rom_component|altrom:srom|q[4] ; dataout          ;
; |signal_gene|address[0]                                                                    ; |signal_gene|address[0]                                                           ; data_out0        ;
; |signal_gene|address[0]                                                                    ; |signal_gene|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0]       ; cout             ;
; |signal_gene|address[1]                                                                    ; |signal_gene|address[1]                                                           ; data_out0        ;