📄 signal_gene.map.rpt
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; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 1 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_a7h ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+--------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_mult:Mult0|mult_0f01:auto_generated|lpm_add_sub:op_1 ;
+------------------------+-------------+--------------------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+--------------------------------------------------------------------+
; LPM_WIDTH ; 6 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 1 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_87h ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+--------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance ;
+---------------------------------------+----------------+
; Name ; Value ;
+---------------------------------------+----------------+
; Number of entity instances ; 1 ;
; Entity Instance ; lpm_mult:Mult0 ;
; -- LPM_WIDTHA ; 4 ;
; -- LPM_WIDTHB ; 7 ;
; -- LPM_WIDTHP ; 11 ;
; -- LPM_REPRESENTATION ; UNSIGNED ;
; -- INPUT_A_IS_CONSTANT ; NO ;
; -- INPUT_B_IS_CONSTANT ; NO ;
; -- USE_EAB ; OFF ;
; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ;
; -- INPUT_A_FIXED_VALUE ; Bx ;
; -- INPUT_B_FIXED_VALUE ; Bx ;
+---------------------------------------+----------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Tue Dec 30 12:38:55 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off signal_gene -c signal_gene
Info: Found 1 design units, including 1 entities, in source file datarom.v
Info: Found entity 1: datarom
Info: Found 1 design units, including 1 entities, in source file signal_gene.v
Info: Found entity 1: signal_gene
Info: Elaborating entity "signal_gene" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at signal_gene.v(19): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(23): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(36): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(40): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(54): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(58): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(72): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at signal_gene.v(76): truncated value with size 32 to match size of target (8)
Info: Elaborating entity "datarom" for hierarchy "datarom:datarom_component"
Info: Found 1 design units, including 1 entities, in source file e:/altera/70/quartus/libraries/megafunctions/lpm_rom.tdf
Info: Found entity 1: lpm_rom
Info: Elaborating entity "lpm_rom" for hierarchy "datarom:datarom_component|lpm_rom:lpm_rom_component"
Info: Elaborated megafunction instantiation "datarom:datarom_component|lpm_rom:lpm_rom_component"
Info: Found 1 design units, including 1 entities, in source file e:/altera/70/quartus/libraries/megafunctions/altrom.tdf
Info: Found entity 1: altrom
Info: Elaborating entity "altrom" for hierarchy "datarom:datarom_component|lpm_rom:lpm_rom_component|altrom:srom"
Info: Elaborated megafunction instantiation "datarom:datarom_component|lpm_rom:lpm_rom_component|altrom:srom", which is child of megafunction instantiation "datarom:datarom_component|lpm_rom:lpm_rom_component"
Info: Instantiated megafunction "datarom:datarom_component|lpm_rom:lpm_rom_component" with the following parameter:
Info: Parameter "intended_device_family" = "ACEX1K"
Info: Parameter "lpm_address_control" = "REGISTERED"
Info: Parameter "lpm_file" = "signal_gene.mif"
Info: Parameter "lpm_outdata" = "UNREGISTERED"
Info: Parameter "lpm_type" = "LPM_ROM"
Info: Parameter "lpm_width" = "8"
Info: Parameter "lpm_widthad" = "9"
Warning: Reduced register "k[7]" with stuck data_in port to stuck value GND
Info: Found 1 design units, including 1 entities, in source file e:/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0"
Info: Found 1 design units, including 1 entities, in source file e:/altera/70/quartus/libraries/megafunctions/addcore.tdf
Info: Found entity 1: addcore
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
Info: Parameter "LPM_WIDTH" = "9"
Info: Parameter "LPM_DIRECTION" = "ADD"
Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file e:/altera/70/quartus/libraries/megafunctions/a_csnbuffer.tdf
Info: Found entity 1: a_csnbuffer
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
Info: Parameter "LPM_WIDTH" = "9"
Info: Parameter "LPM_DIRECTION" = "ADD"
Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
Info: Parameter "LPM_WIDTH" = "9"
Info: Parameter "LPM_DIRECTION" = "ADD"
Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file e:/altera/70/quartus/libraries/megafunctions/altshift.tdf
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