signal_gene.map.rpt

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Analysis & Synthesis report for signal_gene
Tue Dec 30 12:39:40 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Registers Removed During Synthesis
  9. General Register Statistics
 10. Parameter Settings for User Entity Instance: datarom:datarom_component|lpm_rom:lpm_rom_component
 11. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0
 12. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add1
 13. Parameter Settings for Inferred Entity Instance: lpm_mult:Mult0
 14. Parameter Settings for Inferred Entity Instance: lpm_divide:Div0
 15. Parameter Settings for Inferred Entity Instance: lpm_mult:Mult0|mult_0f01:auto_generated|lpm_add_sub:op_3
 16. Parameter Settings for Inferred Entity Instance: lpm_mult:Mult0|mult_0f01:auto_generated|lpm_add_sub:op_1
 17. lpm_mult Parameter Settings by Entity Instance
 18. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; Analysis & Synthesis Summary                                          ;
+-----------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Dec 30 12:39:39 2008   ;
; Quartus II Version          ; 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name               ; signal_gene                             ;
; Top-level Entity Name       ; signal_gene                             ;
; Family                      ; ACEX1K                                  ;
; Total logic elements        ; 192                                     ;
; Total pins                  ; 15                                      ;
; Total memory bits           ; 4,096                                   ;
; Total PLLs                  ; 0                                       ;
+-----------------------------+-----------------------------------------+


+------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                            ;
+----------------------------------------------------------+---------------+---------------+
; Option                                                   ; Setting       ; Default Value ;
+----------------------------------------------------------+---------------+---------------+
; Device                                                   ; EP1K30TC144-3 ;               ;
; Top-level entity name                                    ; signal_gene   ; signal_gene   ;
; Family name                                              ; ACEX1K        ; Stratix       ;
; Create Debugging Nodes for IP Cores                      ; Off           ; Off           ;
; Preserve fewer node names                                ; On            ; On            ;
; Disable OpenCore Plus hardware evaluation                ; Off           ; Off           ;
; Verilog Version                                          ; Verilog_2001  ; Verilog_2001  ;
; VHDL Version                                             ; VHDL93        ; VHDL93        ;
; State Machine Processing                                 ; Auto          ; Auto          ;
; Safe State Machine                                       ; Off           ; Off           ;
; Extract Verilog State Machines                           ; On            ; On            ;
; Extract VHDL State Machines                              ; On            ; On            ;
; Ignore Verilog initial constructs                        ; Off           ; Off           ;
; Add Pass-Through Logic to Inferred RAMs                  ; On            ; On            ;
; NOT Gate Push-Back                                       ; On            ; On            ;
; Power-Up Don't Care                                      ; On            ; On            ;
; Remove Redundant Logic Cells                             ; Off           ; Off           ;
; Remove Duplicate Registers                               ; On            ; On            ;
; Ignore CARRY Buffers                                     ; Off           ; Off           ;
; Ignore CASCADE Buffers                                   ; Off           ; Off           ;
; Ignore GLOBAL Buffers                                    ; Off           ; Off           ;
; Ignore ROW GLOBAL Buffers                                ; Off           ; Off           ;
; Ignore LCELL Buffers                                     ; Off           ; Off           ;
; Ignore SOFT Buffers                                      ; On            ; On            ;
; Limit AHDL Integers to 32 Bits                           ; Off           ; Off           ;
; Auto Implement in ROM                                    ; Off           ; Off           ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K     ; Area          ; Area          ;
; Carry Chain Length -- FLEX 10K                           ; 32            ; 32            ;
; Cascade Chain Length                                     ; 2             ; 2             ;
; Auto Carry Chains                                        ; On            ; On            ;
; Auto Open-Drain Pins                                     ; On            ; On            ;
; Auto ROM Replacement                                     ; On            ; On            ;
; Auto RAM Replacement                                     ; On            ; On            ;
; Auto Clock Enable Replacement                            ; On            ; On            ;
; Auto Resource Sharing                                    ; Off           ; Off           ;
; Allow Any RAM Size For Recognition                       ; Off           ; Off           ;
; Allow Any ROM Size For Recognition                       ; Off           ; Off           ;
; Ignore translate_off and synthesis_off directives        ; Off           ; Off           ;
; Show Parameter Settings Tables in Synthesis Report       ; On            ; On            ;
; HDL message level                                        ; Level2        ; Level2        ;
; Suppress Register Optimization Related Messages          ; Off           ; Off           ;
; Number of Removed Registers Reported in Synthesis Report ; 100           ; 100           ;
; Use smart compilation                                    ; Off           ; Off           ;
+----------------------------------------------------------+---------------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                   ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                         ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------+
; datarom.v                        ; yes             ; User Verilog HDL File        ; d:/我的文档/桌面/signal_gene/datarom.v                               ;
; signal_gene.v                    ; yes             ; User Verilog HDL File        ; d:/我的文档/桌面/signal_gene/signal_gene.v                           ;
; lpm_rom.tdf                      ; yes             ; Megafunction                 ; e:/altera/70/quartus/libraries/megafunctions/lpm_rom.tdf             ;
; altrom.inc                       ; yes             ; Megafunction                 ; e:/altera/70/quartus/libraries/megafunctions/altrom.inc              ;
; aglobal70.inc                    ; yes             ; Megafunction                 ; e:/altera/70/quartus/libraries/megafunctions/aglobal70.inc           ;
; altrom.tdf                       ; yes             ; Megafunction                 ; e:/altera/70/quartus/libraries/megafunctions/altrom.tdf              ;
; memmodes.inc                     ; yes             ; Megafunction                 ; e:/altera/70/quartus/libraries/others/maxplus2/memmodes.inc          ;
; lpm_decode.inc                   ; yes             ; Megafunction                 ; e:/altera/70/quartus/libraries/megafunctions/lpm_decode.inc          ;
; lpm_mux.inc                      ; yes             ; Megafunction                 ; e:/altera/70/quartus/libraries/megafunctions/lpm_mux.inc             ;
; altqpram.inc                     ; yes             ; Megafunction                 ; e:/altera/70/quartus/libraries/megafunctions/altqpram.inc            ;
; altsyncram.inc                   ; yes             ; Megafunction                 ; e:/altera/70/quartus/libraries/megafunctions/altsyncram.inc          ;
; lpm_add_sub.tdf                  ; yes             ; Megafunction                 ; e:/altera/70/quartus/libraries/megafunctions/lpm_add_sub.tdf         ;
; addcore.inc                      ; yes             ; Megafunction                 ; e:/altera/70/quartus/libraries/megafunctions/addcore.inc             ;