signal_gene.map.summary

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Analysis & Synthesis Status : Successful - Tue Dec 30 12:39:39 2008
Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
Revision Name : signal_gene
Top-level Entity Name : signal_gene
Family : ACEX1K
Total logic elements : 192
Total pins : 15
Total memory bits : 4,096
Total PLLs : 0