signal_gene.v

powerbuild学习重要资料 请下载

module signal_gene(inclock,q_out,control,i);
input inclock;
output[7:0]q_out;
input[1:0]control;
input[3:0]i;
reg[8:0]address;
wire[7:0]q_out;
reg[7:0]m,k;
datarom datarom_component(.address (address),.inclock (inclock),.q (q_out));
always @(posedge inclock)
begin
case(control)
0:begin
if(control==1)address<=128;
if(control==2)address<=256;
if(control==3)address<=384;
if(i==0||i==1)
begin
address<=address+1;
if(address>=127) address<=0;
end
else begin
k<=127/i;m<=i*k;
address<=address+i;
if(address>=m)address<=0;
end
end
1:begin
if(control==0)address<=0;
if(control==2)address<=256;
if(control==3)address<=384;
if(address<128)address<=128;
else begin
if(i==0||i==1)
begin
address<=address+1;
if(address==255)address<=128;
end
else begin
k<=127/i;m<=i*k;
address<=address+i;
if(address>=(m+128))address<=128;
end
end
end
2:begin
if(control==0)address<=0;
if(control==1)address<=128;
if(control==3)address<=384;
if(address<256)address<=256;
else begin
if(i==0||i==1)
begin
address<=address+1;
if(address==383)address<=256;
end
else begin
k<=127/i;m<=i*k;
address<=address+i;
if(address>=(m+256))address<=256;
end
end
end
3:begin
if(control==1)address<=128;
if(control==2)address<=256;
if(control==3)address<=384;
if(address<384)address<=384;
else begin
if(i==0||i==1)
begin
address<=address+1;
if(address==511)address<=384;
end
else begin
k<=127/i;m<=i*k;
address<=address+i;
if(address>=(m+384))address<=384;
end
end
end
endcase
end
endmodule