24l01software.c

用51单片机的并行IO口模拟SPI总线

//******************************************************************// 
//***********************nRF24L01***********************************// 
//******************************************************************// 
// SPI(nRF24L01) commands 
#define READ_REG        0x00  // Define read command to register 
#define WRITE_REG       0x20  // Define write command to register 
#define RD_RX_PLOAD     0x61  // Define RX payload register address 
#define WR_TX_PLOAD     0xA0  // Define TX payload register address 
#define FLUSH_TX        0xE1  // Define flush TX register command 
#define FLUSH_RX        0xE2  // Define flush RX register command 
#define REUSE_TX_PL     0xE3  // Define reuse TX payload register command 
#define NOP1            0xFF  // Define No Operation,used to read status register 

// SPI(nRF24L01) registers(addresses) 
#define CONFIG          0x00  // 'Config' register address 
#define EN_AA           0x01  // 'Enable Auto Acknowledgment' register address 
#define EN_RXADDR       0x02  // 'Enabled RX addresses' register address 
#define SETUP_AW        0x03  // 'Setup address width' register address 
#define SETUP_RETR      0x04  // 'Setup Auto. Retrans' register address 
#define RF_CH           0x05  // 'RF channel' register address 
#define RF_SETUP        0x06  // 'RF setup' register address 
#define STATUS          0x07  // 'Status' register address 
#define OBSERVE_TX      0x08  // 'Observe TX' register address 
#define CD              0x09  // 'Carrier Detect' register address 
#define RX_ADDR_P0      0x0A  // 'RX address pipe0' register address 
#define RX_ADDR_P1      0x0B  // 'RX address pipe1' register address 
#define RX_ADDR_P2      0x0C  // 'RX address pipe2' register address 
#define RX_ADDR_P3      0x0D  // 'RX address pipe3' register address 
#define RX_ADDR_P4      0x0E  // 'RX address pipe4' register address 
#define RX_ADDR_P5      0x0F  // 'RX address pipe5' register address 
#define TX_ADDR         0x10  // 'TX address' register address 
#define RX_PW_P0        0x11  // 'RX payload width, pipe0' register address 
#define RX_PW_P1        0x12  // 'RX payload width, pipe1' register address 
#define RX_PW_P2        0x13  // 'RX payload width, pipe2' register address 
#define RX_PW_P3        0x14  // 'RX payload width, pipe3' register address 
#define RX_PW_P4        0x15  // 'RX payload width, pipe4' register address 
#define RX_PW_P5        0x16  // 'RX payload width, pipe5' register address 
#define FIFO_STATUS     0x17  // 'FIFO Status Register' register address 

//**action declaration**// 
#define CE_0 PORTC &= ~(1<<PORTC5); 
#define CE_1 PORTC |=  (1<<PORTC5); 

//**function declaration**// 
unsigned char SPI_Read_Reg(unsigned char reg_addr); 
unsigned char SPI_Write_Reg(unsigned char reg_addr,unsigned char reg_val); 
unsigned char SPI_Write_Command(unsigned char Command); 
void SPI_Read_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes); 
void SPI_Write_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes); 
void PTX_Config(void); 
void ConfigChk(void); 
void PRX_Config(void); 
//**********************************************************// 
//SPI_Read_Reg();SPI_Write_Reg();SPI_Write_Command(); 
//SPI_Read_Buf();SPI_Write_Buf(); 
//**********************************************************// 
//**SPI_Read_Reg**// 
unsigned char SPI_Read_Reg(unsigned char reg_addr) 
{ 
  unsigned char reg_val; 
   
  CSN_0; 
  SPI_MasterTransmit(reg_addr);           // Select register to read from.. 
  reg_val = SPI_MasterReceive();          // ..then read registervalue                                  
  CSN_1; 
   
  return(reg_val);                        // return register value 
} 
//**SPI_Write_Reg**// 
unsigned char SPI_Write_Reg(unsigned char reg_addr,unsigned char reg_val) 
{ 
  unsigned char status; 

  CSN_0; 
  status=SPI_MasterTransmit(reg_addr);   // select register 
  SPI_MasterTransmit(reg_val);           // ..and write value to it.. 
  CSN_1; 
   
  return(status);                        // return nRF24L01 status byte 
} 

//**SPI_Write_Command()**// 
unsigned char SPI_Write_Command(unsigned char Command) 
{ 
  unsigned char status; 
   
  CSN_0; 
  status = SPI_MasterTransmit(Command);   //Write commmand 
  CSN_1; 
   
  return(status);                         // return nRF24L01 status byte 
} 
//**SPI_Read_Buf**// 
void SPI_Read_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes) 
{ 
  unsigned char byte_ctr; 

  SPI_MasterTransmit(reg); 
  for(byte_ctr=0;byte_ctr<bytes;byte_ctr++) 
      pBuf[byte_ctr] = SPI_MasterReceive(); 
} 
//**SPI_Write_Buf**// 
void SPI_Write_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes) 
{ 
  unsigned char byte_ctr; 

  SPI_MasterTransmit(reg); 
  for(byte_ctr=0; byte_ctr<bytes; byte_ctr++) 
      SPI_MasterTransmit(*pBuf++); 
} 
//**PRX_Config()**// 
//**Standby-1 mode for TX mode 
void Stdby4Tx_Config() 
{ 
 SPI_Write_Command(FLUSH_TX); 
  
 SPI_Write_Reg(WRITE_REG+CONFIG,0x58);//power down,0101 1000 
 SPI_Write_Reg(WRITE_REG+EN_AA,0x00); //disable auto ack 
 SPI_Write_Reg(WRITE_REG+EN_RXADDR,0x01);//enable data receive pipe 0 
 SPI_Write_Reg(WRITE_REG+RX_PW_P0,0x0F);//15 bytes payload 
 SPI_Write_Reg(WRITE_REG+STATUS,0x7E);//clr the interrupt 
  
 SPI_Write_Reg(WRITE_REG+CONFIG,0x5A);//Standby-1 mode,0101 1010 
} 
//**PRX_Config()**// 
//**Standby-1 mode for RX mode 
void Stdby4Rx_Config() 
{  
 SPI_Write_Command(FLUSH_TX); 
  
 SPI_Write_Reg(WRITE_REG+CONFIG,0x39);//power down,0011 1001 
 SPI_Write_Reg(WRITE_REG+EN_AA,0x00); //disable auto ack 
 SPI_Write_Reg(WRITE_REG+EN_RXADDR,0x01);//enable data receive pipe 0 
 SPI_Write_Reg(WRITE_REG+RX_PW_P0,0x0F);//15 bytes payload 
 SPI_Write_Reg(WRITE_REG+STATUS,0x7E);//clr the interrupt 
  
 SPI_Write_Reg(WRITE_REG+CONFIG,0x3B);//PRX mode,0011 1011 
} 
//**PTX_ConfigChk()**// 
void ConfigChk(void) 
{ 
 unsigned char reg_val;  
 reg_val=SPI_Read_Reg(CONFIG);   USART_Transmit(reg_val); 
 reg_val=SPI_Read_Reg(EN_AA);    USART_Transmit(reg_val); 
 reg_val=SPI_Read_Reg(EN_RXADDR);USART_Transmit(reg_val); 
 reg_val=SPI_Read_Reg(RX_PW_P0); USART_Transmit(reg_val);  
} 
//**RF_Transmit**// 
void RF_Transmit(unsigned char *TxDataBuf) 
{ 
 unsigned char temp,i; 
  
 SPI_Write_Command(FLUSH_TX); 
  
 CSN_0; 
 SPI_MasterTransmit(WR_TX_PLOAD); 
 for(i=0;i<15;i++) 
     SPI_MasterTransmit(TxDataBuf[i]); 
 CSN_1; 
  
 CE_1; //activate transmitter  
 Delayus(20); //minimum 10 us for TX mode setup,actual 160us 
 CE_0; //After transmit the data, return to standby-1 mode 
  
 Delayus(150);//this is essential,why?TX setting needs 130us!!! 
  
 SPI_Write_Reg(WRITE_REG+STATUS,0x20);//clr the TX_DS interrupt 
 SPI_Write_Command(FLUSH_TX); 
} 
//**RF_Receive()**// 
void RF_Receive(unsigned char *RxDataBuf) 
{ 
 unsigned char temp,i; 
  
 CSN_0; 
 SPI_MasterTransmit(RD_RX_PLOAD); 
 for(i=0;i<15;i++) 
     { 
      temp=SPI_MasterReceive(); 
          //USART_Transmit(temp); 
          RxDataBuf[i] = temp; 
         } 
 CSN_1; 
  
 SPI_Write_Reg(WRITE_REG+STATUS,0x40);//clr the RX_DR interrupt 
 SPI_Write_Command(FLUSH_RX); 
} 
//******************************************************************// 
//********************** nRF24L01 over *****************************// 
//******************************************************************//