📄 m500auc.lst
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291 2 if (status == MI_NOTAGERR || status == MI_ACCESSTIMEOUT)
292 2 {
293 3 status = MI_OK;
294 3 }
295 2 }
296 1 //reset command register - no response from tag
297 1 WriteIO(RegCommand,PCD_IDLE);
298 1 return status;
299 1 }
300
301 ///////////////////////////////////////////////////////////////////////
302 // Reset the MF RC500
303 ///////////////////////////////////////////////////////////////////////
C51 COMPILER V7.02a M500AUC 06/23/2006 09:38:38 PAGE 6
304 char M500PcdReset(void)
305 {
306 1 char idata status = MI_OK;
307 1 unsigned int idata timecnt=0;
308 1
309 1 RC500RST = 0;
310 1 delay_1ms(25);
311 1 RC500RST = 1;
312 1 delay_50us(200);
313 1 RC500RST = 0;
314 1 delay_50us(50);
315 1 timecnt=1000;
316 1 while ((ReadIO(RegCommand) & 0x3F) && timecnt--);
317 1 if(!timecnt)
318 1 {
319 2 status = MI_RESETERR;
320 2 }
321 1 if (status == MI_OK)
322 1 {
323 2 //WriteIO(RegPage,0x80);
324 2 if (ReadIO(RegCommand) != 0x00)
325 2 {
326 3 status = MI_INTERFACEERR;
327 3 }
328 2 }
329 1 return status;
330 1 }
331
332 ///////////////////////////////////////////////////////////////////////
333 // Configures the MF RC500
334 ///////////////////////////////////////////////////////////////////////
335 char M500PcdConfig(void)
336 {
337 1 char idata status;
338 1
339 1 if ((status = M500PcdReset()) == MI_OK)
340 1 {
341 2 WriteIO(RegClockQControl,0x00);
342 2 WriteIO(RegClockQControl,0x40);
343 2 delay_50us(2);
344 2 ClearBitMask(RegClockQControl,0x40);
345 2 WriteIO(RegBitPhase,0xAD);
346 2 WriteIO(RegRxThreshold,0xFF);
347 2 WriteIO(RegRxControl2,0x01);
348 2 WriteIO(RegFIFOLevel,0x1A);
349 2 WriteIO(RegTimerControl,0x02);
350 2 WriteIO(RegIRqPinConfig,0x03);
351 2 M500PcdRfReset(1);
352 2 }
353 1 return status;
354 1 }
355
356 ///////////////////////////////////////////////////////////////////////
357 // Select Command defined in ISO14443(MIFARE)
358 ///////////////////////////////////////////////////////////////////////
359 char M500PcdMfOutSelect(unsigned char type)
360 {
361 1 WriteIO(RegMfOutSelect,type&0x7);
362 1 return MI_OK;
363 1 }
364
365 ///////////////////////////////////////////////////////////////////////
C51 COMPILER V7.02a M500AUC 06/23/2006 09:38:38 PAGE 7
366 // Request Command defined in ISO14443(MIFARE)
367 // Request,Anticoll,Select,return CardType(2 bytes)+CardSerialNo(4 bytes)
368 // 寻卡，防冲突，选择卡 返回卡类型（2 bytes）+ 卡系列号(4 bytes)
369 ///////////////////////////////////////////////////////////////////////
370 char M500PiccCommonRequest(unsigned char req_code,unsigned char *atq)
371 {
372 1 char idata status = MI_OK;
373 1
374 1 M500PcdSetTmo(3);
375 1 WriteIO(RegChannelRedundancy,0x03);
376 1 ClearBitMask(RegControl,0x08);
377 1 WriteIO(RegBitFraming,0x07);
378 1 SetBitMask(RegTxControl,0x03);
379 1 ResetInfo(MInfo);
380 1 SerBuffer[0] = req_code;
381 1 MInfo.nBytesToSend = 1;
382 1
383 1 status = M500PcdCmd(PCD_TRANSCEIVE,SerBuffer,&MInfo);
384 1 if (status)
385 1 {
386 2 *atq = 0;
387 2 }
388 1 else
389 1 {
390 2 if (MInfo.nBitsReceived != 16)
391 2 {
392 3 *atq = 0;
393 3 status = MI_BITCOUNTERR;
394 3 }
395 2 else
396 2 {
397 3 status = MI_OK;
398 3 memcpy(atq,SerBuffer,2);
399 3 }
400 2 }
401 1 return status;
402 1 }
403
404 ///////////////////////////////////////////////////////////////////
405 // Cascaded Anti-Collision Command defined in ISO14443(MIFARE)
406 // 防冲突 读卡的系列号 MLastSelectedSnr
407 ///////////////////////////////////////////////////////////////////
408 char M500PiccCascAnticoll (unsigned char bcnt,unsigned char *snr)
409 {
410 1 char idata status = MI_OK;
411 1 char idata snr_in[5];//snr_in[4];
412 1 char idata nbytes = 0;
413 1 char idata nbits = 0;
414 1 char idata complete = 0;
415 1 char idata i = 0;
416 1 char idata byteOffset = 0;
417 1 unsigned char dummyShift1;
418 1 unsigned char dummyShift2;
419 1
420 1 M500PcdSetTmo(106);
421 1 memcpy(snr_in,snr,5);//memcpy(snr_in,snr,4);
422 1
423 1 WriteIO(RegDecoderControl,0x28);
424 1 ClearBitMask(RegControl,0x08);
425 1 complete = 0;
426 1 while (!complete && (status == MI_OK) )
427 1 {
C51 COMPILER V7.02a M500AUC 06/23/2006 09:38:38 PAGE 8
428 2 ResetInfo(MInfo);
429 2 WriteIO(RegChannelRedundancy,0x03);
430 2 nbits = bcnt % 8;
431 2 if(nbits)
432 2 {
433 3 WriteIO(RegBitFraming,nbits << 4| nbits);
434 3 nbytes = bcnt / 8 + 1;
435 3 if (nbits == 7)
436 3 {
437 4 MInfo.cmd = PICC_ANTICOLL1;
438 4 WriteIO(RegBitFraming,nbits);
439 4 }
440 3 }
441 2 else
442 2 {
443 3 nbytes = bcnt / 8;
444 3 }
445 2 SerBuffer[0] = 0x93;
446 2 SerBuffer[1] = 0x20 + ((bcnt/8) << 4) + nbits;
447 2
448 2 for (i = 0; i < nbytes; i++)
449 2 {
450 3 SerBuffer[i + 2] = snr_in[i];
451 3 }
452 2 MInfo.nBytesToSend = 2 + nbytes;
453 2
454 2 status = M500PcdCmd(PCD_TRANSCEIVE,SerBuffer,&MInfo);
455 2 if (nbits == 7)
456 2 {
457 3 dummyShift1 = 0x00;
458 3 for (i = 0; i < MInfo.nBytesReceived; i++)
459 3 {
460 4 dummyShift2 = SerBuffer[i];
461 4 SerBuffer[i] = (dummyShift1 >> (i+1)) | (SerBuffer[i] << (7-i));
462 4 dummyShift1 = dummyShift2;
463 4 }
464 3 MInfo.nBitsReceived -= MInfo.nBytesReceived;
465 3 if ( MInfo.collPos ) MInfo.collPos += 7 - (MInfo.collPos + 6) / 9;
466 3 }
467 2 if ( status == MI_OK || status == MI_COLLERR)
468 2 {
469 3 if ( MInfo.nBitsReceived != (40 - bcnt) )
470 3 {
471 4 status = MI_BITCOUNTERR;
472 4 }
473 3 else
474 3 {
475 4 byteOffset = 0;
476 4 if( nbits != 0 )
477 4 {
478 5 snr_in[nbytes - 1] = snr_in[nbytes - 1] | SerBuffer[0];
479 5 byteOffset = 1;
480 5 }
481 4
482 4 for ( i =0; i < (4 - nbytes); i++)
483 4 {
484 5 snr_in[nbytes + i] = SerBuffer[i + byteOffset];
485 5 }
486 4
487 4 if (status != MI_COLLERR )
488 4 {
489 5 dummyShift2 = snr_in[0] ^ snr_in[1] ^ snr_in[2] ^ snr_in[3];
C51 COMPILER V7.02a M500AUC 06/23/2006 09:38:38 PAGE 9
490 5 dummyShift1 = SerBuffer[MInfo.nBytesReceived - 1];
491 5 if (dummyShift2 != dummyShift1)
492 5 {
493 6 status = MI_SERNRERR;
494 6 }
495 5 else
496 5 {
497 6 complete = 1;
498 6 }
499 5 }
500 4 else
501 4 {
502 5 bcnt = bcnt + MInfo.collPos - nbits;
503 5 status = MI_OK;
504 5 }
505 4 }
506 3 }
507 2 }
508 1 if (status == MI_OK)
509 1 {
510 2 snr_in[4]=dummyShift1;
511 2 memcpy(snr,snr_in,5);
512 2 }
513 1 else
514 1 {
515 2 memcpy(snr,"00000",5);
516 2 }
517 1 ClearBitMask(RegDecoderControl,0x20);
518 1
519 1 return status;
520 1 }
521
522 ///////////////////////////////////////////////////////////////////////
523 // Reset Rf Card
524 ///////////////////////////////////////////////////////////////////////
525 char M500PcdRfReset(unsigned char ms)
526 {
527 1 char idata status = MI_OK;
528 1
529 1 if(ms)
530 1 {
531 2 ClearBitMask(RegTxControl,0x03);
532 2 delay_1ms(2);
533 2 SetBitMask(RegTxControl,0x03);
534 2 }
535 1 else
536 1 {
537 2 ClearBitMask(RegTxControl,0x03);
538 2 }
539 1 return status;
540 1 }
541
542 #pragma noaregs
543
544 ///////////////////////////////////////////////////////////////////////
545 // Delay 50us
546 ///////////////////////////////////////////////////////////////////////
547 void delay_50us(unsigned char _50us)
548 {
549 1 while(_50us--)
550 1 {
551 2 _nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
C51 COMPILER V7.02a M500AUC 06/23/2006 09:38:38 PAGE 10
552 2 _nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
553 2 _nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
554 2 _nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
555 2 _nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
556 2 _nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
557 2 _nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
558 2 _nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
559 2 }
560 1 }
561
562 ///////////////////////////////////////////////////////////////////////
563 // Delay 1ms
564 ///////////////////////////////////////////////////////////////////////
565 void delay_1ms(unsigned char _1ms)
566 {
567 1 #ifndef NO_TIMER2
RCAP2LH = RCAP2_1ms;
T2LH = RCAP2_1ms;
TR2 = TRUE;
while (_1ms--)
{
while (!TF2);
TF2 = FALSE;
}
TR2 = FALSE;
#else
579 1 while (_1ms--)
580 1 {
581 2 delay_50us(20);
582 2 }
583 1 #endif
584 1 }
585
586 ///////////////////////////////////////////////////////////////////////
587 // Delay 10ms
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