delay_ram.v

turbo码_verilog_编码源文件

module delay_ram(//input:
				
                 data_clk,//global
                 bitin,//related upper module
					  wen, //related cntrlunit
					  addrw,//related cntrlunit
					  delay_addrr,//related cntrlunit
					  //output:
					  bitout//related to followed module
					  );


input data_clk;
input bitin;
input [13:0] addrw;
input wen;
input [13:0] delay_addrr;
output bitout;

wire bitin;
wire [13:0] addrw;
wire wen;
wire [13:0] delay_addrr;
wire bitout;


RAMB16_S1_S1 delay(.DOA(),//[0:0] DOA; 
                   .DOB(bitout), //[0:0] DOB;
                   .ADDRA(addrw),//[13:0] ADDRA; 
                   .CLKA(data_clk), 
                   .DIA(bitin), //[0:0] DIA; 
                   .ENA(wen), 
                   .SSRA(1'b0), 
                   .WEA(1'b1), 
                   .ADDRB(delay_addrr),//[13:0] ADDRB; 
                   .CLKB(data_clk), 
                   .DIB(),//[0:0] DIB;
                   .ENB(1'b1), 
                   .SSRB(1'b0), 
                   .WEB(1'b0)
				       );



endmodule