c16.hier_info

基于QU II开发的8051处理器,有基本的操作指令.

CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
CLK => 12.CLK
D1 => 19.DATAIN
Q2 <= 18.DB_MAX_OUTPUT_PORT_TYPE
D2 => 18.DATAIN
Q3 <= 17.DB_MAX_OUTPUT_PORT_TYPE
D3 => 17.DATAIN
Q4 <= 16.DB_MAX_OUTPUT_PORT_TYPE
D4 => 16.DATAIN
Q5 <= 15.DB_MAX_OUTPUT_PORT_TYPE
D5 => 15.DATAIN
Q6 <= 14.DB_MAX_OUTPUT_PORT_TYPE
D6 => 14.DATAIN
Q7 <= 13.DB_MAX_OUTPUT_PORT_TYPE
D7 => 13.DATAIN
Q8 <= 12.DB_MAX_OUTPUT_PORT_TYPE
D8 => 12.DATAIN


|c16|ir:inst2|74273:inst1
Q1 <= 19.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 19.ACLR
CLRN => 18.ACLR
CLRN => 17.ACLR
CLRN => 16.ACLR
CLRN => 15.ACLR
CLRN => 14.ACLR
CLRN => 13.ACLR
CLRN => 12.ACLR
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
CLK => 12.CLK
D1 => 19.DATAIN
Q2 <= 18.DB_MAX_OUTPUT_PORT_TYPE
D2 => 18.DATAIN
Q3 <= 17.DB_MAX_OUTPUT_PORT_TYPE
D3 => 17.DATAIN
Q4 <= 16.DB_MAX_OUTPUT_PORT_TYPE
D4 => 16.DATAIN
Q5 <= 15.DB_MAX_OUTPUT_PORT_TYPE
D5 => 15.DATAIN
Q6 <= 14.DB_MAX_OUTPUT_PORT_TYPE
D6 => 14.DATAIN
Q7 <= 13.DB_MAX_OUTPUT_PORT_TYPE
D7 => 13.DATAIN
Q8 <= 12.DB_MAX_OUTPUT_PORT_TYPE
D8 => 12.DATAIN


|c16|timer:inst
m7 <= 74273:125.Q7
CLK => 3.CLK
CLK => 4.CLK
CLK => 2.CLK
CLK => 1.CLK
CLK => 74273:125.CLK
HALT => 74273:125.CLRN
m <= 74273:125.Q8
m6 <= 74273:125.Q6
m3 <= 74273:125.Q3
m2 <= 74273:125.Q2
m4 <= 74273:125.Q4
m5 <= 74273:125.Q5
m1 <= 74273:125.Q1


|c16|timer:inst|74273:125
Q1 <= 19.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 19.ACLR
CLRN => 18.ACLR
CLRN => 17.ACLR
CLRN => 16.ACLR
CLRN => 15.ACLR
CLRN => 14.ACLR
CLRN => 13.ACLR
CLRN => 12.ACLR
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
CLK => 12.CLK
D1 => 19.DATAIN
Q2 <= 18.DB_MAX_OUTPUT_PORT_TYPE
D2 => 18.DATAIN
Q3 <= 17.DB_MAX_OUTPUT_PORT_TYPE
D3 => 17.DATAIN
Q4 <= 16.DB_MAX_OUTPUT_PORT_TYPE
D4 => 16.DATAIN
Q5 <= 15.DB_MAX_OUTPUT_PORT_TYPE
D5 => 15.DATAIN
Q6 <= 14.DB_MAX_OUTPUT_PORT_TYPE
D6 => 14.DATAIN
Q7 <= 13.DB_MAX_OUTPUT_PORT_TYPE
D7 => 13.DATAIN
Q8 <= 12.DB_MAX_OUTPUT_PORT_TYPE
D8 => 12.DATAIN


|c16|uIR:inst6
uPC[0] <= 74273:inst.Q1
uPC[1] <= 74273:inst.Q2
uPC[2] <= 74273:inst.Q3
uPC[3] <= 74273:inst.Q4
uPC[4] <= 74273:inst.Q5
uPC[5] <= 74273:inst.Q6
uPC[6] <= 74273:inst.Q7
uPC[7] <= 74273:inst.Q8
uPC[8] <= 74273:inst1.Q1
uPC[9] <= 74273:inst1.Q2
uPC[10] <= 74273:inst1.Q3
uPC[11] <= 74273:inst1.Q4
uPC[12] <= 74273:inst1.Q5
uPC[13] <= 74273:inst1.Q6
uPC[14] <= 74273:inst1.Q7
uPC[15] <= 74273:inst1.Q8
uPC[16] <= 74273:inst2.Q1
uPC[17] <= 74273:inst2.Q2
uPC[18] <= 74273:inst2.Q3
uPC[19] <= 74273:inst2.Q4
uPC[20] <= 74273:inst2.Q5
uPC[21] <= 74273:inst2.Q6
uPC[22] <= 74273:inst2.Q7
uPC[23] <= 74273:inst2.Q8
uPC[24] <= 74273:inst3.Q1
uPC[25] <= 74273:inst3.Q2
uPC[26] <= 74273:inst3.Q3
uPC[27] <= 74273:inst3.Q4
uPC[28] <= 74273:inst3.Q5
uPC[29] <= 74273:inst3.Q6
uPC[30] <= 74273:inst3.Q7
uPC[31] <= 74273:inst3.Q8
uPC[32] <= 74273:inst4.Q1
uPC[33] <= 74273:inst4.Q2
uPC[34] <= 74273:inst4.Q3
uPC[35] <= 74273:inst4.Q4
uPC[36] <= 74273:inst4.Q5
uPC[37] <= 74273:inst4.Q6
uPC[38] <= 74273:inst4.Q7
uPC[39] <= 74273:inst4.Q8
D[0] => 74273:inst.D1
D[1] => 74273:inst.D2
D[2] => 74273:inst.D3
D[3] => 74273:inst.D4
D[4] => 74273:inst.D5
D[5] => 74273:inst.D6
D[6] => 74273:inst.D7
D[7] => 74273:inst.D8
D[8] => 74273:inst1.D1
D[9] => 74273:inst1.D2
D[10] => 74273:inst1.D3
D[11] => 74273:inst1.D4
D[12] => 74273:inst1.D5
D[13] => 74273:inst1.D6
D[14] => 74273:inst1.D7
D[15] => 74273:inst1.D8
D[16] => 74273:inst2.D1
D[17] => 74273:inst2.D2
D[18] => 74273:inst2.D3
D[19] => 74273:inst2.D4
D[20] => 74273:inst2.D5
D[21] => 74273:inst2.D6
D[22] => 74273:inst2.D7
D[23] => 74273:inst2.D8
D[24] => 74273:inst3.D1
D[25] => 74273:inst3.D2
D[26] => 74273:inst3.D3
D[27] => 74273:inst3.D4
D[28] => 74273:inst3.D5
D[29] => 74273:inst3.D6
D[30] => 74273:inst3.D7
D[31] => 74273:inst3.D8
D[32] => 74273:inst4.D1
D[33] => 74273:inst4.D2
D[34] => 74273:inst4.D3
D[35] => 74273:inst4.D4
D[36] => 74273:inst4.D5
D[37] => 74273:inst4.D6
D[38] => 74273:inst4.D7
D[39] => 74273:inst4.D8
CPuIR => 74273:inst4.CLK
CPuIR => 74273:inst3.CLK
CPuIR => 74273:inst2.CLK
CPuIR => 74273:inst1.CLK
CPuIR => 74273:inst.CLK
0-uIR => inst5.IN0


|c16|uIR:inst6|74273:inst4
Q1 <= 19.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 19.ACLR
CLRN => 18.ACLR
CLRN => 17.ACLR
CLRN => 16.ACLR
CLRN => 15.ACLR
CLRN => 14.ACLR
CLRN => 13.ACLR
CLRN => 12.ACLR
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
CLK => 12.CLK
D1 => 19.DATAIN
Q2 <= 18.DB_MAX_OUTPUT_PORT_TYPE
D2 => 18.DATAIN
Q3 <= 17.DB_MAX_OUTPUT_PORT_TYPE
D3 => 17.DATAIN
Q4 <= 16.DB_MAX_OUTPUT_PORT_TYPE
D4 => 16.DATAIN
Q5 <= 15.DB_MAX_OUTPUT_PORT_TYPE
D5 => 15.DATAIN
Q6 <= 14.DB_MAX_OUTPUT_PORT_TYPE
D6 => 14.DATAIN
Q7 <= 13.DB_MAX_OUTPUT_PORT_TYPE
D7 => 13.DATAIN
Q8 <= 12.DB_MAX_OUTPUT_PORT_TYPE
D8 => 12.DATAIN


|c16|uIR:inst6|74273:inst3
Q1 <= 19.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 19.ACLR
CLRN => 18.ACLR
CLRN => 17.ACLR
CLRN => 16.ACLR
CLRN => 15.ACLR
CLRN => 14.ACLR
CLRN => 13.ACLR
CLRN => 12.ACLR
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
CLK => 12.CLK
D1 => 19.DATAIN
Q2 <= 18.DB_MAX_OUTPUT_PORT_TYPE
D2 => 18.DATAIN
Q3 <= 17.DB_MAX_OUTPUT_PORT_TYPE
D3 => 17.DATAIN
Q4 <= 16.DB_MAX_OUTPUT_PORT_TYPE
D4 => 16.DATAIN
Q5 <= 15.DB_MAX_OUTPUT_PORT_TYPE
D5 => 15.DATAIN
Q6 <= 14.DB_MAX_OUTPUT_PORT_TYPE
D6 => 14.DATAIN
Q7 <= 13.DB_MAX_OUTPUT_PORT_TYPE
D7 => 13.DATAIN
Q8 <= 12.DB_MAX_OUTPUT_PORT_TYPE
D8 => 12.DATAIN


|c16|uIR:inst6|74273:inst2
Q1 <= 19.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 19.ACLR
CLRN => 18.ACLR
CLRN => 17.ACLR
CLRN => 16.ACLR
CLRN => 15.ACLR
CLRN => 14.ACLR
CLRN => 13.ACLR
CLRN => 12.ACLR
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
CLK => 12.CLK
D1 => 19.DATAIN
Q2 <= 18.DB_MAX_OUTPUT_PORT_TYPE
D2 => 18.DATAIN
Q3 <= 17.DB_MAX_OUTPUT_PORT_TYPE
D3 => 17.DATAIN
Q4 <= 16.DB_MAX_OUTPUT_PORT_TYPE
D4 => 16.DATAIN
Q5 <= 15.DB_MAX_OUTPUT_PORT_TYPE
D5 => 15.DATAIN
Q6 <= 14.DB_MAX_OUTPUT_PORT_TYPE
D6 => 14.DATAIN
Q7 <= 13.DB_MAX_OUTPUT_PORT_TYPE
D7 => 13.DATAIN
Q8 <= 12.DB_MAX_OUTPUT_PORT_TYPE
D8 => 12.DATAIN


|c16|uIR:inst6|74273:inst1
Q1 <= 19.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 19.ACLR
CLRN => 18.ACLR
CLRN => 17.ACLR
CLRN => 16.ACLR
CLRN => 15.ACLR
CLRN => 14.ACLR
CLRN => 13.ACLR
CLRN => 12.ACLR
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
CLK => 12.CLK
D1 => 19.DATAIN
Q2 <= 18.DB_MAX_OUTPUT_PORT_TYPE
D2 => 18.DATAIN
Q3 <= 17.DB_MAX_OUTPUT_PORT_TYPE
D3 => 17.DATAIN
Q4 <= 16.DB_MAX_OUTPUT_PORT_TYPE
D4 => 16.DATAIN
Q5 <= 15.DB_MAX_OUTPUT_PORT_TYPE
D5 => 15.DATAIN
Q6 <= 14.DB_MAX_OUTPUT_PORT_TYPE
D6 => 14.DATAIN
Q7 <= 13.DB_MAX_OUTPUT_PORT_TYPE
D7 => 13.DATAIN
Q8 <= 12.DB_MAX_OUTPUT_PORT_TYPE
D8 => 12.DATAIN


|c16|uIR:inst6|74273:inst
Q1 <= 19.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 19.ACLR
CLRN => 18.ACLR
CLRN => 17.ACLR
CLRN => 16.ACLR
CLRN => 15.ACLR
CLRN => 14.ACLR
CLRN => 13.ACLR
CLRN => 12.ACLR
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
CLK => 12.CLK
D1 => 19.DATAIN
Q2 <= 18.DB_MAX_OUTPUT_PORT_TYPE
D2 => 18.DATAIN
Q3 <= 17.DB_MAX_OUTPUT_PORT_TYPE
D3 => 17.DATAIN
Q4 <= 16.DB_MAX_OUTPUT_PORT_TYPE
D4 => 16.DATAIN
Q5 <= 15.DB_MAX_OUTPUT_PORT_TYPE
D5 => 15.DATAIN
Q6 <= 14.DB_MAX_OUTPUT_PORT_TYPE
D6 => 14.DATAIN
Q7 <= 13.DB_MAX_OUTPUT_PORT_TYPE
D7 => 13.DATAIN
Q8 <= 12.DB_MAX_OUTPUT_PORT_TYPE
D8 => 12.DATAIN


|c16|urom:inst9
OUT[0] <= LPM_ROM:inst.q[0]
OUT[1] <= LPM_ROM:inst.q[1]
OUT[2] <= LPM_ROM:inst.q[2]
OUT[3] <= LPM_ROM:inst.q[3]
OUT[4] <= LPM_ROM:inst.q[4]
OUT[5] <= LPM_ROM:inst.q[5]
OUT[6] <= LPM_ROM:inst.q[6]
OUT[7] <= LPM_ROM:inst.q[7]
OUT[8] <= LPM_ROM:inst.q[8]
OUT[9] <= LPM_ROM:inst.q[9]
OUT[10] <= LPM_ROM:inst.q[10]
OUT[11] <= LPM_ROM:inst.q[11]
OUT[12] <= LPM_ROM:inst.q[12]
OUT[13] <= LPM_ROM:inst.q[13]
OUT[14] <= LPM_ROM:inst.q[14]
OUT[15] <= LPM_ROM:inst.q[15]
OUT[16] <= LPM_ROM:inst.q[16]
OUT[17] <= LPM_ROM:inst.q[17]
OUT[18] <= LPM_ROM:inst.q[18]
OUT[19] <= LPM_ROM:inst.q[19]
OUT[20] <= LPM_ROM:inst.q[20]
OUT[21] <= LPM_ROM:inst.q[21]
OUT[22] <= LPM_ROM:inst.q[22]
OUT[23] <= LPM_ROM:inst.q[23]
OUT[24] <= LPM_ROM:inst.q[24]
OUT[25] <= LPM_ROM:inst.q[25]
OUT[26] <= LPM_ROM:inst.q[26]
OUT[27] <= LPM_ROM:inst.q[27]
OUT[28] <= LPM_ROM:inst.q[28]
OUT[29] <= LPM_ROM:inst.q[29]
OUT[30] <= LPM_ROM:inst.q[30]
OUT[31] <= LPM_ROM:inst.q[31]
OUT[32] <= LPM_ROM:inst.q[32]
OUT[33] <= LPM_ROM:inst.q[33]
OUT[34] <= LPM_ROM:inst.q[34]
OUT[35] <= LPM_ROM:inst.q[35]
OUT[36] <= LPM_ROM:inst.q[36]
OUT[37] <= LPM_ROM:inst.q[37]
OUT[38] <= LPM_ROM:inst.q[38]
OUT[39] <= LPM_ROM:inst.q[39]
clk => LPM_ROM:inst.outclock
ADD[0] => LPM_ROM:inst.address[0]
ADD[1] => LPM_ROM:inst.address[1]
ADD[2] => LPM_ROM:inst.address[2]
ADD[3] => LPM_ROM:inst.address[3]
ADD[4] => LPM_ROM:inst.address[4]
ADD[5] => LPM_ROM:inst.address[5]
ADD[6] => LPM_ROM:inst.address[6]
ADD[7] => LPM_ROM:inst.address[7]
ADD[8] => LPM_ROM:inst.address[8]
ADD[9] => LPM_ROM:inst.address[9]
ADD[10] => LPM_ROM:inst.address[10]
ADD[11] => LPM_ROM:inst.address[11]


|c16|urom:inst9|LPM_ROM:inst
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
address[8] => altrom:srom.address[8]
address[9] => altrom:srom.address[9]
address[10] => altrom:srom.address[10]
address[11] => altrom:srom.address[11]
inclock => ~NO_FANOUT~
outclock => altrom:srom.clocko
memenab => otri[39].OE
memenab => otri[38].OE
memenab => otri[37].OE
memenab => otri[36].OE
memenab => otri[35].OE
memenab => otri[34].OE
memenab => otri[33].OE
memenab => otri[32].OE
memenab => otri[31].OE
memenab => otri[30].OE
memenab => otri[29].OE
memenab => otri[28].OE
memenab => otri[27].OE
memenab => otri[26].OE
memenab => otri[25].OE
memenab => otri[24].OE
memenab => otri[23].OE
memenab => otri[22].OE
memenab => otri[21].OE
memenab => otri[20].OE
memenab => otri[19].OE
memenab => otri[18].OE
memenab => otri[17].OE
memenab => otri[16].OE
memenab => otri[15].OE
memenab => otri[14].OE
memenab => otri[13].OE
memenab => otri[12].OE
memenab => otri[11].OE
memenab => otri[10].OE
memenab => otri[9].OE
memenab => otri[8].OE
memenab => otri[7].OE
memenab => otri[6].OE
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= otri[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= otri[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= otri[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= otri[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= otri[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= otri[12].DB_MAX_OUTPUT_PORT_TYPE
q[13] <= otri[13].DB_MAX_OUTPUT_PORT_TYPE
q[14] <= otri[14].DB_MAX_OUTPUT_PORT_TYPE
q[15] <= otri[15].DB_MAX_OUTPUT_PORT_TYPE
q[16] <= otri[16].DB_MAX_OUTPUT_PORT_TYPE
q[17] <= otri[17].DB_MAX_OUTPUT_PORT_TYPE
q[18] <= otri[18].DB_MAX_OUTPUT_PORT_TYPE
q[19] <= otri[19].DB_MAX_OUTPUT_PORT_TYPE
q[20] <= otri[20].DB_MAX_OUTPUT_PORT_TYPE
q[21] <= otri[21].DB_MAX_OUTPUT_PORT_TYPE
q[22] <= otri[22].DB_MAX_OUTPUT_PORT_TYPE
q[23] <= otri[23].DB_MAX_OUTPUT_PORT_TYPE
q[24] <= otri[24].DB_MAX_OUTPUT_PORT_TYPE
q[25] <= otri[25].DB_MAX_OUTPUT_PORT_TYPE
q[26] <= otri[26].DB_MAX_OUTPUT_PORT_TYPE
q[27] <= otri[27].DB_MAX_OUTPUT_PORT_TYPE
q[28] <= otri[28].DB_MAX_OUTPUT_PORT_TYPE
q[29] <= otri[29].DB_MAX_OUTPUT_PORT_TYPE
q[30] <= otri[30].DB_MAX_OUTPUT_PORT_TYPE
q[31] <= otri[31].DB_MAX_OUTPUT_PORT_TYPE
q[32] <= otri[32].DB_MAX_OUTPUT_PORT_TYPE
q[33] <= otri[33].DB_MAX_OUTPUT_PORT_TYPE
q[34] <= otri[34].DB_MAX_OUTPUT_PORT_TYPE
q[35] <= otri[35].DB_MAX_OUTPUT_PORT_TYPE
q[36] <= otri[36].DB_MAX_OUTPUT_PORT_TYPE
q[37] <= otri[37].DB_MAX_OUTPUT_PORT_TYPE
q[38] <= otri[38].DB_MAX_OUTPUT_PORT_TYPE
q[39] <= otri[39].DB_MAX_OUTPUT_PORT_TYPE


|c16|urom:inst9|LPM_ROM:inst|altrom:srom
address[0] => altsyncram:rom_block.address_a[0]
address[1] => altsyncram:rom_block.address_a[1]
address[2] => altsyncram:rom_block.address_a[2]
address[3] => altsyncram:rom_block.address_a[3]
address[4] => altsyncram:rom_block.address_a[4]
address[5] => altsyncram:rom_block.address_a[5]
address[6] => altsyncram:rom_block.address_a[6]
address[7] => altsyncram:rom_block.address_a[7]
address[8] => altsyncram:rom_block.address_a[8]
address[9] => altsyncram:rom_block.address_a[9]
address[10] => altsyncram:rom_block.address_a[10]
address[11] => altsyncram:rom_block.address_a[11]
clocki => ~NO_FANOUT~
clocko => altsyncram:rom_block.clock0
q[0] <= altsyncram:rom_block.q_a[0]
q[1] <= altsyncram:rom_block.q_a[1]
q[2] <= altsyncram:rom_block.q_a[2]
q[3] <= altsyncram:rom_block.q_a[3]
q[4] <= altsyncram:rom_block.q_a[4]
q[5] <= altsyncram:rom_block.q_a[5]
q[6] <= altsyncram:rom_block.q_a[6]
q[7] <= altsyncram:rom_block.q_a[7]
q[8] <= altsyncram:rom_block.q_a[8]
q[9] <= al