c16.hier_info

基于QU II开发的8051处理器,有基本的操作指令.

address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clock1 => ram_block1a5.CLK1
clock1 => ram_block1a6.CLK1
clock1 => ram_block1a7.CLK1
clock1 => ram_block1a8.CLK1
clock1 => ram_block1a9.CLK1
clock1 => ram_block1a10.CLK1
clock1 => ram_block1a11.CLK1
clock1 => ram_block1a12.CLK1
clock1 => ram_block1a13.CLK1
clock1 => ram_block1a14.CLK1
clock1 => ram_block1a15.CLK1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT
q_a[12] <= ram_block1a12.PORTADATAOUT
q_a[13] <= ram_block1a13.PORTADATAOUT
q_a[14] <= ram_block1a14.PORTADATAOUT
q_a[15] <= ram_block1a15.PORTADATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a13.PORTAWE
wren_a => ram_block1a14.PORTAWE
wren_a => ram_block1a15.PORTAWE


|c16|mem:inst3|74273:inst
Q1 <= 19.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 19.ACLR
CLRN => 18.ACLR
CLRN => 17.ACLR
CLRN => 16.ACLR
CLRN => 15.ACLR
CLRN => 14.ACLR
CLRN => 13.ACLR
CLRN => 12.ACLR
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
CLK => 12.CLK
D1 => 19.DATAIN
Q2 <= 18.DB_MAX_OUTPUT_PORT_TYPE
D2 => 18.DATAIN
Q3 <= 17.DB_MAX_OUTPUT_PORT_TYPE
D3 => 17.DATAIN
Q4 <= 16.DB_MAX_OUTPUT_PORT_TYPE
D4 => 16.DATAIN
Q5 <= 15.DB_MAX_OUTPUT_PORT_TYPE
D5 => 15.DATAIN
Q6 <= 14.DB_MAX_OUTPUT_PORT_TYPE
D6 => 14.DATAIN
Q7 <= 13.DB_MAX_OUTPUT_PORT_TYPE
D7 => 13.DATAIN
Q8 <= 12.DB_MAX_OUTPUT_PORT_TYPE
D8 => 12.DATAIN


|c16|mem:inst3|74244:inst6
2Y4 <= 26.DB_MAX_OUTPUT_PORT_TYPE
2A4 => 26.DATAIN
2GN => 33.IN0
2Y3 <= 27.DB_MAX_OUTPUT_PORT_TYPE
2A3 => 27.DATAIN
2Y2 <= 31.DB_MAX_OUTPUT_PORT_TYPE
2A2 => 31.DATAIN
2Y1 <= 36.DB_MAX_OUTPUT_PORT_TYPE
2A1 => 36.DATAIN
1Y1 <= 1.DB_MAX_OUTPUT_PORT_TYPE
1A1 => 1.DATAIN
1GN => 4.IN0
1Y2 <= 6.DB_MAX_OUTPUT_PORT_TYPE
1A2 => 6.DATAIN
1Y3 <= 10.DB_MAX_OUTPUT_PORT_TYPE
1A3 => 10.DATAIN
1Y4 <= 11.DB_MAX_OUTPUT_PORT_TYPE
1A4 => 11.DATAIN


|c16|mem:inst3|74273:inst5
Q1 <= 19.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 19.ACLR
CLRN => 18.ACLR
CLRN => 17.ACLR
CLRN => 16.ACLR
CLRN => 15.ACLR
CLRN => 14.ACLR
CLRN => 13.ACLR
CLRN => 12.ACLR
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
CLK => 12.CLK
D1 => 19.DATAIN
Q2 <= 18.DB_MAX_OUTPUT_PORT_TYPE
D2 => 18.DATAIN
Q3 <= 17.DB_MAX_OUTPUT_PORT_TYPE
D3 => 17.DATAIN
Q4 <= 16.DB_MAX_OUTPUT_PORT_TYPE
D4 => 16.DATAIN
Q5 <= 15.DB_MAX_OUTPUT_PORT_TYPE
D5 => 15.DATAIN
Q6 <= 14.DB_MAX_OUTPUT_PORT_TYPE
D6 => 14.DATAIN
Q7 <= 13.DB_MAX_OUTPUT_PORT_TYPE
D7 => 13.DATAIN
Q8 <= 12.DB_MAX_OUTPUT_PORT_TYPE
D8 => 12.DATAIN


|c16|1612:inst5
O7 <= 74244:23.2Y4
PC1 => 74161:1.LDN
PC1 => 74161:2.LDN
D0 => 74161:1.A
D3 => 74161:1.D
D2 => 74161:1.C
D1 => 74161:1.B
CPPC => 74161:1.CLK
CPPC => 74161:2.CLK
PC-BUS => 74244:23.1GN
PC-BUS => 74244:23.2GN
D4 => 74161:2.A
D7 => 74161:2.D
D6 => 74161:2.C
D5 => 74161:2.B
O2 <= 74244:23.1Y3
O4 <= 74244:23.2Y1
O1 <= 74244:23.1Y2
O0 <= 74244:23.1Y1
O3 <= 74244:23.1Y4
O5 <= 74244:23.2Y2
O6 <= 74244:23.2Y3


|c16|1612:inst5|74244:23
2Y4 <= 26.DB_MAX_OUTPUT_PORT_TYPE
2A4 => 26.DATAIN
2GN => 33.IN0
2Y3 <= 27.DB_MAX_OUTPUT_PORT_TYPE
2A3 => 27.DATAIN
2Y2 <= 31.DB_MAX_OUTPUT_PORT_TYPE
2A2 => 31.DATAIN
2Y1 <= 36.DB_MAX_OUTPUT_PORT_TYPE
2A1 => 36.DATAIN
1Y1 <= 1.DB_MAX_OUTPUT_PORT_TYPE
1A1 => 1.DATAIN
1GN => 4.IN0
1Y2 <= 6.DB_MAX_OUTPUT_PORT_TYPE
1A2 => 6.DATAIN
1Y3 <= 10.DB_MAX_OUTPUT_PORT_TYPE
1A3 => 10.DATAIN
1Y4 <= 11.DB_MAX_OUTPUT_PORT_TYPE
1A4 => 11.DATAIN


|c16|1612:inst5|74161:1
clk => f74161:sub.clk
ldn => f74161:sub.ldn
clrn => f74161:sub.clrn
enp => f74161:sub.enp
ent => f74161:sub.ent
d => f74161:sub.d
c => f74161:sub.c
b => f74161:sub.b
a => f74161:sub.a
qd <= f74161:sub.qd
qc <= f74161:sub.qc
qb <= f74161:sub.qb
qa <= f74161:sub.qa
rco <= f74161:sub.rco


|c16|1612:inst5|74161:1|f74161:sub
RCO <= 105.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 110.ACLR
CLRN => 99.ACLR
CLRN => 87.ACLR
CLRN => 9.ACLR
CLK => 110.CLK
CLK => 99.CLK
CLK => 87.CLK
CLK => 9.CLK
D => 113.IN0
LDN => 117.IN0
LDN => 77.IN1
LDN => 86.IN1
LDN => 98.IN1
LDN => 108.IN1
ENP => 106.IN0
ENP => 96.IN0
ENP => 89.IN0
ENP => 79.IN0
C => 101.IN0
B => 91.IN0
A => 76.IN0
ENT => 82.DATAIN
QD <= 110.DB_MAX_OUTPUT_PORT_TYPE
QC <= 99.DB_MAX_OUTPUT_PORT_TYPE
QB <= 87.DB_MAX_OUTPUT_PORT_TYPE
QA <= 9.DB_MAX_OUTPUT_PORT_TYPE


|c16|1612:inst5|74161:2
clk => f74161:sub.clk
ldn => f74161:sub.ldn
clrn => f74161:sub.clrn
enp => f74161:sub.enp
ent => f74161:sub.ent
d => f74161:sub.d
c => f74161:sub.c
b => f74161:sub.b
a => f74161:sub.a
qd <= f74161:sub.qd
qc <= f74161:sub.qc
qb <= f74161:sub.qb
qa <= f74161:sub.qa
rco <= f74161:sub.rco


|c16|1612:inst5|74161:2|f74161:sub
RCO <= 105.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 110.ACLR
CLRN => 99.ACLR
CLRN => 87.ACLR
CLRN => 9.ACLR
CLK => 110.CLK
CLK => 99.CLK
CLK => 87.CLK
CLK => 9.CLK
D => 113.IN0
LDN => 117.IN0
LDN => 77.IN1
LDN => 86.IN1
LDN => 98.IN1
LDN => 108.IN1
ENP => 106.IN0
ENP => 96.IN0
ENP => 89.IN0
ENP => 79.IN0
C => 101.IN0
B => 91.IN0
A => 76.IN0
ENT => 82.DATAIN
QD <= 110.DB_MAX_OUTPUT_PORT_TYPE
QC <= 99.DB_MAX_OUTPUT_PORT_TYPE
QB <= 87.DB_MAX_OUTPUT_PORT_TYPE
QA <= 9.DB_MAX_OUTPUT_PORT_TYPE


|c16|iopr:inst10
O0 <= 74244:inst.1Y1
D1 => 74244:inst.1A2
D1 => 74244:inst12.1A2
D3 => 74244:inst.1A4
D0 => 74244:inst.1A1
D0 => 74244:inst12.1A1
D2 => 74244:inst.1A3
BUS => inst13.IN0
D6 => 74244:inst.2A3
D4 => 74244:inst.2A1
D7 => 74244:inst.2A4
D5 => 74244:inst.2A2
O1 <= 74244:inst.1Y2
O2 <= 74244:inst.1Y3
O3 <= 74244:inst.1Y4
O4 <= 74244:inst.2Y1
O5 <= 74244:inst.2Y2
O6 <= 74244:inst.2Y3
O7 <= 74244:inst.2Y4
A <= 74244:inst12.1Y1
REG => inst14.IN0
B <= 74244:inst12.1Y2
H[0] <= inst1[0].DB_MAX_OUTPUT_PORT_TYPE
H[1] <= inst1[1].DB_MAX_OUTPUT_PORT_TYPE
H[2] <= inst1[2].DB_MAX_OUTPUT_PORT_TYPE
H[3] <= inst1[3].DB_MAX_OUTPUT_PORT_TYPE
H[4] <= inst1[4].DB_MAX_OUTPUT_PORT_TYPE
H[5] <= inst1[5].DB_MAX_OUTPUT_PORT_TYPE
H[6] <= inst1[6].DB_MAX_OUTPUT_PORT_TYPE
H[7] <= inst1[7].DB_MAX_OUTPUT_PORT_TYPE


|c16|iopr:inst10|74244:inst
2Y4 <= 26.DB_MAX_OUTPUT_PORT_TYPE
2A4 => 26.DATAIN
2GN => 33.IN0
2Y3 <= 27.DB_MAX_OUTPUT_PORT_TYPE
2A3 => 27.DATAIN
2Y2 <= 31.DB_MAX_OUTPUT_PORT_TYPE
2A2 => 31.DATAIN
2Y1 <= 36.DB_MAX_OUTPUT_PORT_TYPE
2A1 => 36.DATAIN
1Y1 <= 1.DB_MAX_OUTPUT_PORT_TYPE
1A1 => 1.DATAIN
1GN => 4.IN0
1Y2 <= 6.DB_MAX_OUTPUT_PORT_TYPE
1A2 => 6.DATAIN
1Y3 <= 10.DB_MAX_OUTPUT_PORT_TYPE
1A3 => 10.DATAIN
1Y4 <= 11.DB_MAX_OUTPUT_PORT_TYPE
1A4 => 11.DATAIN


|c16|iopr:inst10|74244:inst12
2Y4 <= 26.DB_MAX_OUTPUT_PORT_TYPE
2A4 => 26.DATAIN
2GN => 33.IN0
2Y3 <= 27.DB_MAX_OUTPUT_PORT_TYPE
2A3 => 27.DATAIN
2Y2 <= 31.DB_MAX_OUTPUT_PORT_TYPE
2A2 => 31.DATAIN
2Y1 <= 36.DB_MAX_OUTPUT_PORT_TYPE
2A1 => 36.DATAIN
1Y1 <= 1.DB_MAX_OUTPUT_PORT_TYPE
1A1 => 1.DATAIN
1GN => 4.IN0
1Y2 <= 6.DB_MAX_OUTPUT_PORT_TYPE
1A2 => 6.DATAIN
1Y3 <= 10.DB_MAX_OUTPUT_PORT_TYPE
1A3 => 10.DATAIN
1Y4 <= 11.DB_MAX_OUTPUT_PORT_TYPE
1A4 => 11.DATAIN


|c16|ir:inst2
IOUT[0] <= 74273:inst.Q1
IOUT[1] <= 74273:inst.Q2
IOUT[2] <= 74273:inst.Q3
IOUT[3] <= 74273:inst.Q4
IOUT[4] <= 74273:inst.Q5
IOUT[5] <= 74273:inst.Q6
IOUT[6] <= 74273:inst.Q7
IOUT[7] <= 74273:inst.Q8
IOUT[8] <= 74273:inst1.Q1
IOUT[9] <= 74273:inst1.Q2
IOUT[10] <= 74273:inst1.Q3
IOUT[11] <= 74273:inst1.Q4
IOUT[12] <= 74273:inst1.Q5
IOUT[13] <= 74273:inst1.Q6
IOUT[14] <= 74273:inst1.Q7
IOUT[15] <= 74273:inst1.Q8
BUS[0] => 74273:inst.D1
BUS[1] => 74273:inst.D2
BUS[2] => 74273:inst.D3
BUS[3] => 74273:inst.D4
BUS[4] => 74273:inst.D5
BUS[5] => 74273:inst.D6
BUS[6] => 74273:inst.D7
BUS[7] => 74273:inst.D8
BUS[8] => 74273:inst1.D1
BUS[9] => 74273:inst1.D2
BUS[10] => 74273:inst1.D3
BUS[11] => 74273:inst1.D4
BUS[12] => 74273:inst1.D5
BUS[13] => 74273:inst1.D6
BUS[14] => 74273:inst1.D7
BUS[15] => 74273:inst1.D8
CPIR => 74273:inst.CLK
CPIR => 74273:inst1.CLK
0_IR => inst6.IN0


|c16|ir:inst2|74273:inst
Q1 <= 19.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 19.ACLR
CLRN => 18.ACLR
CLRN => 17.ACLR
CLRN => 16.ACLR
CLRN => 15.ACLR
CLRN => 14.ACLR
CLRN => 13.ACLR
CLRN => 12.ACLR
CLK => 19.CLK