c16.hier_info

基于QU II开发的8051处理器,有基本的操作指令.

C_BUS => 74244:inst4.2GN
C_BUS => 74244:inst5.1GN
C_BUS => 74244:inst5.2GN
O12 <= 74244:inst5.1Y4
L_M => 7408:inst8.2
O15 <= 74244:inst5.1Y1
O14 <= 74244:inst5.1Y2
O13 <= 74244:inst5.1Y3
O11 <= 74244:inst5.2Y1
O10 <= 74244:inst5.2Y2
O9 <= 74244:inst5.2Y3
O8 <= 74244:inst5.2Y4
O7 <= 74244:inst4.1Y1
O6 <= 74244:inst4.1Y2
O5 <= 74244:inst4.1Y3
O3 <= 74244:inst4.2Y1
O2 <= 74244:inst4.2Y2
O1 <= 74244:inst4.2Y3
O0 <= 74244:inst4.2Y4


|c16|reg2:inst8|74244:inst4
2Y4 <= 26.DB_MAX_OUTPUT_PORT_TYPE
2A4 => 26.DATAIN
2GN => 33.IN0
2Y3 <= 27.DB_MAX_OUTPUT_PORT_TYPE
2A3 => 27.DATAIN
2Y2 <= 31.DB_MAX_OUTPUT_PORT_TYPE
2A2 => 31.DATAIN
2Y1 <= 36.DB_MAX_OUTPUT_PORT_TYPE
2A1 => 36.DATAIN
1Y1 <= 1.DB_MAX_OUTPUT_PORT_TYPE
1A1 => 1.DATAIN
1GN => 4.IN0
1Y2 <= 6.DB_MAX_OUTPUT_PORT_TYPE
1A2 => 6.DATAIN
1Y3 <= 10.DB_MAX_OUTPUT_PORT_TYPE
1A3 => 10.DATAIN
1Y4 <= 11.DB_MAX_OUTPUT_PORT_TYPE
1A4 => 11.DATAIN


|c16|reg2:inst8|74198:instl
QH <= 120.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 120.ACLR
CLRN => 119.ACLR
CLRN => 118.ACLR
CLRN => 117.ACLR
CLRN => 116.ACLR
CLRN => 115.ACLR
CLRN => 114.ACLR
CLRN => 113.ACLR
CLK => 120.CLK
CLK => 119.CLK
CLK => 118.CLK
CLK => 117.CLK
CLK => 116.CLK
CLK => 115.CLK
CLK => 114.CLK
CLK => 113.CLK
S1 => 160.IN0
S1 => 84.IN1
S1 => 83.IN0
S1 => 88.IN1
S1 => 87.IN0
S1 => 92.IN1
S1 => 91.IN0
S1 => 96.IN1
S1 => 95.IN0
S1 => 100.IN1
S1 => 99.IN0
S1 => 104.IN1
S1 => 103.IN0
S1 => 108.IN1
S1 => 107.IN0
S1 => 112.IN1
S1 => 111.IN0
S0 => 159.IN0
S0 => 110.IN1
S0 => 106.IN1
S0 => 102.IN1
S0 => 98.IN1
S0 => 94.IN1
S0 => 90.IN1
S0 => 86.IN1
S0 => 82.IN1
S0 => 84.IN0
S0 => 88.IN0
S0 => 92.IN0
S0 => 96.IN0
S0 => 100.IN0
S0 => 104.IN0
S0 => 108.IN0
S0 => 112.IN0
SRSI => 82.IN2
A => 84.IN2
B => 88.IN2
C => 92.IN2
D => 96.IN2
E => 100.IN2
F => 104.IN2
G => 108.IN2
H => 112.IN2
SLSI => 111.IN2
QG <= 119.DB_MAX_OUTPUT_PORT_TYPE
QF <= 118.DB_MAX_OUTPUT_PORT_TYPE
QE <= 117.DB_MAX_OUTPUT_PORT_TYPE
QD <= 116.DB_MAX_OUTPUT_PORT_TYPE
QC <= 115.DB_MAX_OUTPUT_PORT_TYPE
QB <= 114.DB_MAX_OUTPUT_PORT_TYPE
QA <= 113.DB_MAX_OUTPUT_PORT_TYPE


|c16|reg2:inst8|74273:inst
Q1 <= 19.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 19.ACLR
CLRN => 18.ACLR
CLRN => 17.ACLR
CLRN => 16.ACLR
CLRN => 15.ACLR
CLRN => 14.ACLR
CLRN => 13.ACLR
CLRN => 12.ACLR
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
CLK => 12.CLK
D1 => 19.DATAIN
Q2 <= 18.DB_MAX_OUTPUT_PORT_TYPE
D2 => 18.DATAIN
Q3 <= 17.DB_MAX_OUTPUT_PORT_TYPE
D3 => 17.DATAIN
Q4 <= 16.DB_MAX_OUTPUT_PORT_TYPE
D4 => 16.DATAIN
Q5 <= 15.DB_MAX_OUTPUT_PORT_TYPE
D5 => 15.DATAIN
Q6 <= 14.DB_MAX_OUTPUT_PORT_TYPE
D6 => 14.DATAIN
Q7 <= 13.DB_MAX_OUTPUT_PORT_TYPE
D7 => 13.DATAIN
Q8 <= 12.DB_MAX_OUTPUT_PORT_TYPE
D8 => 12.DATAIN


|c16|reg2:inst8|74273:inst1
Q1 <= 19.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 19.ACLR
CLRN => 18.ACLR
CLRN => 17.ACLR
CLRN => 16.ACLR
CLRN => 15.ACLR
CLRN => 14.ACLR
CLRN => 13.ACLR
CLRN => 12.ACLR
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
CLK => 12.CLK
D1 => 19.DATAIN
Q2 <= 18.DB_MAX_OUTPUT_PORT_TYPE
D2 => 18.DATAIN
Q3 <= 17.DB_MAX_OUTPUT_PORT_TYPE
D3 => 17.DATAIN
Q4 <= 16.DB_MAX_OUTPUT_PORT_TYPE
D4 => 16.DATAIN
Q5 <= 15.DB_MAX_OUTPUT_PORT_TYPE
D5 => 15.DATAIN
Q6 <= 14.DB_MAX_OUTPUT_PORT_TYPE
D6 => 14.DATAIN
Q7 <= 13.DB_MAX_OUTPUT_PORT_TYPE
D7 => 13.DATAIN
Q8 <= 12.DB_MAX_OUTPUT_PORT_TYPE
D8 => 12.DATAIN


|c16|reg2:inst8|74244:inst5
2Y4 <= 26.DB_MAX_OUTPUT_PORT_TYPE
2A4 => 26.DATAIN
2GN => 33.IN0
2Y3 <= 27.DB_MAX_OUTPUT_PORT_TYPE
2A3 => 27.DATAIN
2Y2 <= 31.DB_MAX_OUTPUT_PORT_TYPE
2A2 => 31.DATAIN
2Y1 <= 36.DB_MAX_OUTPUT_PORT_TYPE
2A1 => 36.DATAIN
1Y1 <= 1.DB_MAX_OUTPUT_PORT_TYPE
1A1 => 1.DATAIN
1GN => 4.IN0
1Y2 <= 6.DB_MAX_OUTPUT_PORT_TYPE
1A2 => 6.DATAIN
1Y3 <= 10.DB_MAX_OUTPUT_PORT_TYPE
1A3 => 10.DATAIN
1Y4 <= 11.DB_MAX_OUTPUT_PORT_TYPE
1A4 => 11.DATAIN


|c16|reg2:inst8|74198:insth
QH <= 120.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 120.ACLR
CLRN => 119.ACLR
CLRN => 118.ACLR
CLRN => 117.ACLR
CLRN => 116.ACLR
CLRN => 115.ACLR
CLRN => 114.ACLR
CLRN => 113.ACLR
CLK => 120.CLK
CLK => 119.CLK
CLK => 118.CLK
CLK => 117.CLK
CLK => 116.CLK
CLK => 115.CLK
CLK => 114.CLK
CLK => 113.CLK
S1 => 160.IN0
S1 => 84.IN1
S1 => 83.IN0
S1 => 88.IN1
S1 => 87.IN0
S1 => 92.IN1
S1 => 91.IN0
S1 => 96.IN1
S1 => 95.IN0
S1 => 100.IN1
S1 => 99.IN0
S1 => 104.IN1
S1 => 103.IN0
S1 => 108.IN1
S1 => 107.IN0
S1 => 112.IN1
S1 => 111.IN0
S0 => 159.IN0
S0 => 110.IN1
S0 => 106.IN1
S0 => 102.IN1
S0 => 98.IN1
S0 => 94.IN1
S0 => 90.IN1
S0 => 86.IN1
S0 => 82.IN1
S0 => 84.IN0
S0 => 88.IN0
S0 => 92.IN0
S0 => 96.IN0
S0 => 100.IN0
S0 => 104.IN0
S0 => 108.IN0
S0 => 112.IN0
SRSI => 82.IN2
A => 84.IN2
B => 88.IN2
C => 92.IN2
D => 96.IN2
E => 100.IN2
F => 104.IN2
G => 108.IN2
H => 112.IN2
SLSI => 111.IN2
QG <= 119.DB_MAX_OUTPUT_PORT_TYPE
QF <= 118.DB_MAX_OUTPUT_PORT_TYPE
QE <= 117.DB_MAX_OUTPUT_PORT_TYPE
QD <= 116.DB_MAX_OUTPUT_PORT_TYPE
QC <= 115.DB_MAX_OUTPUT_PORT_TYPE
QB <= 114.DB_MAX_OUTPUT_PORT_TYPE
QA <= 113.DB_MAX_OUTPUT_PORT_TYPE


|c16|reg2:inst8|7408:inst8
1 <= 4.DB_MAX_OUTPUT_PORT_TYPE
2 => 4.IN0
3 => 4.IN1


|c16|mem:inst3
O0 <= 74244:inst2.1Y1
WR => LPM_RAM_DQ:inst3.inclock
WRE => LPM_RAM_DQ:inst3.we
RD => LPM_RAM_DQ:inst3.outclock
A1 => 74273:inst.D2
A2 => 74273:inst.D3
A0 => 74273:inst.D1
A3 => 74273:inst.D4
A6 => 74273:inst.D7
A5 => 74273:inst.D6
A4 => 74273:inst.D5
A7 => 74273:inst.D8
CPMAR => 74273:inst.CLK
D15 => LPM_RAM_DQ:inst3.data[15]
D14 => LPM_RAM_DQ:inst3.data[14]
D13 => LPM_RAM_DQ:inst3.data[13]
D12 => LPM_RAM_DQ:inst3.data[12]
D11 => LPM_RAM_DQ:inst3.data[11]
D10 => LPM_RAM_DQ:inst3.data[10]
D9 => LPM_RAM_DQ:inst3.data[9]
D8 => LPM_RAM_DQ:inst3.data[8]
D7 => LPM_RAM_DQ:inst3.data[7]
D6 => LPM_RAM_DQ:inst3.data[6]
D5 => LPM_RAM_DQ:inst3.data[5]
D4 => LPM_RAM_DQ:inst3.data[4]
D3 => LPM_RAM_DQ:inst3.data[3]
D2 => LPM_RAM_DQ:inst3.data[2]
D1 => LPM_RAM_DQ:inst3.data[1]
D0 => LPM_RAM_DQ:inst3.data[0]
CPMDR => 74273:inst1.CLK
CPMDR => 74273:inst5.CLK
RAM_BUS => 74244:inst2.1GN
RAM_BUS => 74244:inst2.2GN
RAM_BUS => 74244:inst6.1GN
RAM_BUS => 74244:inst6.2GN
O1 <= 74244:inst2.1Y2
O2 <= 74244:inst2.1Y3
O3 <= 74244:inst2.1Y4
O4 <= 74244:inst2.2Y1
O5 <= 74244:inst2.2Y2
O6 <= 74244:inst2.2Y3
O7 <= 74244:inst2.2Y4
O8 <= 74244:inst6.1Y1
O9 <= 74244:inst6.1Y2
O10 <= 74244:inst6.1Y3
O11 <= 74244:inst6.1Y4
O12 <= 74244:inst6.2Y1
O13 <= 74244:inst6.2Y2
O14 <= 74244:inst6.2Y3
O15 <= 74244:inst6.2Y4


|c16|mem:inst3|74244:inst2
2Y4 <= 26.DB_MAX_OUTPUT_PORT_TYPE
2A4 => 26.DATAIN
2GN => 33.IN0
2Y3 <= 27.DB_MAX_OUTPUT_PORT_TYPE
2A3 => 27.DATAIN
2Y2 <= 31.DB_MAX_OUTPUT_PORT_TYPE
2A2 => 31.DATAIN
2Y1 <= 36.DB_MAX_OUTPUT_PORT_TYPE
2A1 => 36.DATAIN
1Y1 <= 1.DB_MAX_OUTPUT_PORT_TYPE
1A1 => 1.DATAIN
1GN => 4.IN0
1Y2 <= 6.DB_MAX_OUTPUT_PORT_TYPE
1A2 => 6.DATAIN
1Y3 <= 10.DB_MAX_OUTPUT_PORT_TYPE
1A3 => 10.DATAIN
1Y4 <= 11.DB_MAX_OUTPUT_PORT_TYPE
1A4 => 11.DATAIN


|c16|mem:inst3|74273:inst1
Q1 <= 19.DB_MAX_OUTPUT_PORT_TYPE
CLRN => 19.ACLR
CLRN => 18.ACLR
CLRN => 17.ACLR
CLRN => 16.ACLR
CLRN => 15.ACLR
CLRN => 14.ACLR
CLRN => 13.ACLR
CLRN => 12.ACLR
CLK => 19.CLK
CLK => 18.CLK
CLK => 17.CLK
CLK => 16.CLK
CLK => 15.CLK
CLK => 14.CLK
CLK => 13.CLK
CLK => 12.CLK
D1 => 19.DATAIN
Q2 <= 18.DB_MAX_OUTPUT_PORT_TYPE
D2 => 18.DATAIN
Q3 <= 17.DB_MAX_OUTPUT_PORT_TYPE
D3 => 17.DATAIN
Q4 <= 16.DB_MAX_OUTPUT_PORT_TYPE
D4 => 16.DATAIN
Q5 <= 15.DB_MAX_OUTPUT_PORT_TYPE
D5 => 15.DATAIN
Q6 <= 14.DB_MAX_OUTPUT_PORT_TYPE
D6 => 14.DATAIN
Q7 <= 13.DB_MAX_OUTPUT_PORT_TYPE
D7 => 13.DATAIN
Q8 <= 12.DB_MAX_OUTPUT_PORT_TYPE
D8 => 12.DATAIN


|c16|mem:inst3|LPM_RAM_DQ:inst3
data[0] => altram:sram.data[0]
data[1] => altram:sram.data[1]
data[2] => altram:sram.data[2]
data[3] => altram:sram.data[3]
data[4] => altram:sram.data[4]
data[5] => altram:sram.data[5]
data[6] => altram:sram.data[6]
data[7] => altram:sram.data[7]
data[8] => altram:sram.data[8]
data[9] => altram:sram.data[9]
data[10] => altram:sram.data[10]
data[11] => altram:sram.data[11]
data[12] => altram:sram.data[12]
data[13] => altram:sram.data[13]
data[14] => altram:sram.data[14]
data[15] => altram:sram.data[15]
address[0] => altram:sram.address[0]
address[1] => altram:sram.address[1]
address[2] => altram:sram.address[2]
address[3] => altram:sram.address[3]
address[4] => altram:sram.address[4]
address[5] => altram:sram.address[5]
address[6] => altram:sram.address[6]
address[7] => altram:sram.address[7]
inclock => altram:sram.clocki
outclock => altram:sram.clocko
we => altram:sram.we
q[0] <= altram:sram.q[0]
q[1] <= altram:sram.q[1]
q[2] <= altram:sram.q[2]
q[3] <= altram:sram.q[3]
q[4] <= altram:sram.q[4]
q[5] <= altram:sram.q[5]
q[6] <= altram:sram.q[6]
q[7] <= altram:sram.q[7]
q[8] <= altram:sram.q[8]
q[9] <= altram:sram.q[9]
q[10] <= altram:sram.q[10]
q[11] <= altram:sram.q[11]
q[12] <= altram:sram.q[12]
q[13] <= altram:sram.q[13]
q[14] <= altram:sram.q[14]
q[15] <= altram:sram.q[15]


|c16|mem:inst3|LPM_RAM_DQ:inst3|altram:sram
data[0] => altsyncram:ram_block.data_a[0]
data[1] => altsyncram:ram_block.data_a[1]
data[2] => altsyncram:ram_block.data_a[2]
data[3] => altsyncram:ram_block.data_a[3]
data[4] => altsyncram:ram_block.data_a[4]
data[5] => altsyncram:ram_block.data_a[5]
data[6] => altsyncram:ram_block.data_a[6]
data[7] => altsyncram:ram_block.data_a[7]
data[8] => altsyncram:ram_block.data_a[8]
data[9] => altsyncram:ram_block.data_a[9]
data[10] => altsyncram:ram_block.data_a[10]
data[11] => altsyncram:ram_block.data_a[11]
data[12] => altsyncram:ram_block.data_a[12]
data[13] => altsyncram:ram_block.data_a[13]
data[14] => altsyncram:ram_block.data_a[14]
data[15] => altsyncram:ram_block.data_a[15]
address[0] => altsyncram:ram_block.address_a[0]
address[1] => altsyncram:ram_block.address_a[1]
address[2] => altsyncram:ram_block.address_a[2]
address[3] => altsyncram:ram_block.address_a[3]
address[4] => altsyncram:ram_block.address_a[4]
address[5] => altsyncram:ram_block.address_a[5]
address[6] => altsyncram:ram_block.address_a[6]
address[7] => altsyncram:ram_block.address_a[7]
clocki => altsyncram:ram_block.clock0
clocko => altsyncram:ram_block.clock1
q[0] <= altsyncram:ram_block.q_a[0]
q[1] <= altsyncram:ram_block.q_a[1]
q[2] <= altsyncram:ram_block.q_a[2]
q[3] <= altsyncram:ram_block.q_a[3]
q[4] <= altsyncram:ram_block.q_a[4]
q[5] <= altsyncram:ram_block.q_a[5]
q[6] <= altsyncram:ram_block.q_a[6]
q[7] <= altsyncram:ram_block.q_a[7]
q[8] <= altsyncram:ram_block.q_a[8]
q[9] <= altsyncram:ram_block.q_a[9]
q[10] <= altsyncram:ram_block.q_a[10]
q[11] <= altsyncram:ram_block.q_a[11]
q[12] <= altsyncram:ram_block.q_a[12]
q[13] <= altsyncram:ram_block.q_a[13]
q[14] <= altsyncram:ram_block.q_a[14]
q[15] <= altsyncram:ram_block.q_a[15]


|c16|mem:inst3|LPM_RAM_DQ:inst3|altram:sram|altsyncram:ram_block
wren_a => altsyncram_2601:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_2601:auto_generated.data_a[0]
data_a[1] => altsyncram_2601:auto_generated.data_a[1]
data_a[2] => altsyncram_2601:auto_generated.data_a[2]
data_a[3] => altsyncram_2601:auto_generated.data_a[3]
data_a[4] => altsyncram_2601:auto_generated.data_a[4]
data_a[5] => altsyncram_2601:auto_generated.data_a[5]
data_a[6] => altsyncram_2601:auto_generated.data_a[6]
data_a[7] => altsyncram_2601:auto_generated.data_a[7]
data_a[8] => altsyncram_2601:auto_generated.data_a[8]
data_a[9] => altsyncram_2601:auto_generated.data_a[9]
data_a[10] => altsyncram_2601:auto_generated.data_a[10]
data_a[11] => altsyncram_2601:auto_generated.data_a[11]
data_a[12] => altsyncram_2601:auto_generated.data_a[12]
data_a[13] => altsyncram_2601:auto_generated.data_a[13]
data_a[14] => altsyncram_2601:auto_generated.data_a[14]
data_a[15] => altsyncram_2601:auto_generated.data_a[15]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_2601:auto_generated.address_a[0]
address_a[1] => altsyncram_2601:auto_generated.address_a[1]
address_a[2] => altsyncram_2601:auto_generated.address_a[2]
address_a[3] => altsyncram_2601:auto_generated.address_a[3]
address_a[4] => altsyncram_2601:auto_generated.address_a[4]
address_a[5] => altsyncram_2601:auto_generated.address_a[5]
address_a[6] => altsyncram_2601:auto_generated.address_a[6]
address_a[7] => altsyncram_2601:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_2601:auto_generated.clock0
clock1 => altsyncram_2601:auto_generated.clock1
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_2601:auto_generated.q_a[0]
q_a[1] <= altsyncram_2601:auto_generated.q_a[1]
q_a[2] <= altsyncram_2601:auto_generated.q_a[2]
q_a[3] <= altsyncram_2601:auto_generated.q_a[3]
q_a[4] <= altsyncram_2601:auto_generated.q_a[4]
q_a[5] <= altsyncram_2601:auto_generated.q_a[5]
q_a[6] <= altsyncram_2601:auto_generated.q_a[6]
q_a[7] <= altsyncram_2601:auto_generated.q_a[7]
q_a[8] <= altsyncram_2601:auto_generated.q_a[8]
q_a[9] <= altsyncram_2601:auto_generated.q_a[9]
q_a[10] <= altsyncram_2601:auto_generated.q_a[10]
q_a[11] <= altsyncram_2601:auto_generated.q_a[11]
q_a[12] <= altsyncram_2601:auto_generated.q_a[12]
q_a[13] <= altsyncram_2601:auto_generated.q_a[13]
q_a[14] <= altsyncram_2601:auto_generated.q_a[14]
q_a[15] <= altsyncram_2601:auto_generated.q_a[15]
q_b[0] <= <GND>


|c16|mem:inst3|LPM_RAM_DQ:inst3|altram:sram|altsyncram:ram_block|altsyncram_2601:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR