altsyncram_oqv.tdf

基于QU II开发的8051处理器,有基本的操作指令.

	ram_block1a8 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "ram",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock1",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a9 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "ram",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock1",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a10 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "ram",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock1",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a11 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "ram",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock1",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a12 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "ram",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock1",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a13 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "ram",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock1",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a14 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "ram",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock1",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a15 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "ram",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "clock1",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "off",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 15,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 16,
			RAM_BLOCK_TYPE = "auto"
		);
	address_a_wire[7..0]	: WIRE;

BEGIN 
	ram_block1a[15..0].clk0 = clock0;
	ram_block1a[15..0].clk1 = clock1;
	ram_block1a[0].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[1].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[2].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[3].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[4].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[5].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[6].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[7].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[8].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[9].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[10].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[11].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[12].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[13].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[14].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[15].portaaddr[] = ( address_a_wire[7..0]);
	ram_block1a[0].portadatain[] = ( data_a[0..0]);
	ram_block1a[1].portadatain[] = ( data_a[1..1]);
	ram_block1a[2].portadatain[] = ( data_a[2..2]);
	ram_block1a[3].portadatain[] = ( data_a[3..3]);
	ram_block1a[4].portadatain[] = ( data_a[4..4]);
	ram_block1a[5].portadatain[] = ( data_a[5..5]);
	ram_block1a[6].portadatain[] = ( data_a[6..6]);
	ram_block1a[7].portadatain[] = ( data_a[7..7]);
	ram_block1a[8].portadatain[] = ( data_a[8..8]);
	ram_block1a[9].portadatain[] = ( data_a[9..9]);
	ram_block1a[10].portadatain[] = ( data_a[10..10]);
	ram_block1a[11].portadatain[] = ( data_a[11..11]);
	ram_block1a[12].portadatain[] = ( data_a[12..12]);
	ram_block1a[13].portadatain[] = ( data_a[13..13]);
	ram_block1a[14].portadatain[] = ( data_a[14..14]);
	ram_block1a[15].portadatain[] = ( data_a[15..15]);
	ram_block1a[15..0].portawe = wren_a;
	address_a_wire[] = address_a[];
	q_a[] = ( ram_block1a[15..0].portadataout[0..0]);
END;
--VALID FILE