c16.map.qmsg

基于QU II开发的8051处理器,有基本的操作指令.

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom urom:inst9\|LPM_ROM:inst\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"urom:inst9\|LPM_ROM:inst\|altrom:srom\"" {  } { { "LPM_ROM.tdf" "srom" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 57 3 0 } }  } 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "urom:inst9\|LPM_ROM:inst\|altrom:srom urom:inst9\|LPM_ROM:inst " "Info: Issued messages during elaboration of megafunction \"urom:inst9\|LPM_ROM:inst\|altrom:srom\", which is child of megafunction \"urom:inst9\|LPM_ROM:inst\"" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 57 3 0 } } { "urom.bdf" "" { Schematic "E:/c16final/urom.bdf" { { 136 320 432 232 "inst" "" } } } }  } 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "urom:inst9\|LPM_ROM:inst " "Info: Instantiated megafunction \"urom:inst9\|LPM_ROM:inst\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_ADDRESS_CONTROL UNREGISTERED " "Info: Parameter \"LPM_ADDRESS_CONTROL\" = \"UNREGISTERED\"" {  } {  } 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_FILE rom.mif " "Info: Parameter \"LPM_FILE\" = \"rom.mif\"" {  } {  } 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_OUTDATA REGISTERED " "Info: Parameter \"LPM_OUTDATA\" = \"REGISTERED\"" {  } {  } 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 40 " "Info: Parameter \"LPM_WIDTH\" = \"40\"" {  } {  } 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHAD 12 " "Info: Parameter \"LPM_WIDTHAD\" = \"12\"" {  } {  } 0}  } { { "urom.bdf" "" { Schematic "E:/c16final/urom.bdf" { { 136 320 432 232 "inst" "" } } } }  } 0}
{ "Warning" "WTDFX_ASSERTION" "Can't convert ROM for Cyclone II device family using altsyncram megafunction -- implementing ROM using benchmarking mode by moving output registers to the input side. Power-up states and behavior may be different. " "Warning: Assertion warning: Can't convert ROM for Cyclone II device family using altsyncram megafunction -- implementing ROM using benchmarking mode by moving output registers to the input side. Power-up states and behavior may be different." {  } { { "altrom.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altrom.tdf" 194 2 0 } } { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 57 3 0 } } { "urom.bdf" "" { Schematic "E:/c16final/urom.bdf" { { 136 320 432 232 "inst" "" } } } } { "c16.bdf" "" { Schematic "E:/c16final/c16.bdf" { { 96 -8 168 192 "inst9" "" } } } }  } 0}
{ "Info" "ITDFX_ASSERTION" "Clocko port is used as clock for the address input port " "Info: Assertion information: Clocko port is used as clock for the address input port" {  } { { "altrom.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altrom.tdf" 283 8 0 } } { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 57 3 0 } } { "urom.bdf" "" { Schematic "E:/c16final/urom.bdf" { { 136 320 432 232 "inst" "" } } } } { "c16.bdf" "" { Schematic "E:/c16final/c16.bdf" { { 96 -8 168 192 "inst9" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram urom:inst9\|LPM_ROM:inst\|altrom:srom\|altsyncram:rom_block " "Info: Elaborating entity \"altsyncram\" for hierarchy \"urom:inst9\|LPM_ROM:inst\|altrom:srom\|altsyncram:rom_block\"" {  } { { "altrom.tdf" "rom_block" { Text "e:/altera/quartus50/libraries/megafunctions/altrom.tdf" 102 8 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_dqm.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_dqm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_dqm " "Info: Found entity 1: altsyncram_dqm" {  } { { "db/altsyncram_dqm.tdf" "" { Text "E:/c16final/db/altsyncram_dqm.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_dqm urom:inst9\|LPM_ROM:inst\|altrom:srom\|altsyncram:rom_block\|altsyncram_dqm:auto_generated " "Info: Elaborating entity \"altsyncram_dqm\" for hierarchy \"urom:inst9\|LPM_ROM:inst\|altrom:srom\|altsyncram:rom_block\|altsyncram_dqm:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uPC uPC:inst7 " "Info: Elaborating entity \"uPC\" for hierarchy \"uPC:inst7\"" {  } { { "c16.bdf" "inst7" { Schematic "E:/c16final/c16.bdf" { { 0 720 840 160 "inst7" "" } } } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Warning: Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Warning: Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "urom:inst9\|lpm_rom:inst\|altrom:srom\|altsyncram:rom_block\|altsyncram_dqm:auto_generated\|ram_block1a2 " "Warning: Synthesized away node \"urom:inst9\|lpm_rom:inst\|altrom:srom\|altsyncram:rom_block\|altsyncram_dqm:auto_generated\|ram_block1a2\"" {  } { { "db/altsyncram_dqm.tdf" "" { Text "E:/c16final/db/altsyncram_dqm.tdf" 81 2 0 } } { "altsyncram.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } } { "altrom.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altrom.tdf" 102 8 0 } } { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 57 3 0 } } { "urom.bdf" "" { Schematic "E:/c16final/urom.bdf" { { 136 320 432 232 "inst" "" } } } } { "c16.bdf" "" { Schematic "E:/c16final/c16.bdf" { { 96 -8 168 192 "inst9" "" } } } }  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "11 " "Info: Ignored 11 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_CARRY" "11 " "Info: Ignored 11 CARRY buffer(s)" {  } {  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[39\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[39\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[38\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[38\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[37\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[37\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[36\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[36\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[35\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[35\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[34\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[34\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[33\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[33\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[32\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[32\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[31\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[31\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[30\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[30\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[29\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[29\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[28\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[28\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[27\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[27\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[26\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[26\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[25\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[25\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[24\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[24\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[23\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[23\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[22\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[22\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[21\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[21\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[20\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[20\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[19\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[19\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[18\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[18\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[17\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[17\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[16\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[16\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[15\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[15\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[14\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[14\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[13\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[13\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[12\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[12\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[11\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[11\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[10\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[10\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[9\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[9\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[8\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[8\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[7\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[7\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[6\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[6\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[5\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[5\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[4\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[4\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[3\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[3\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[1\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[1\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "urom:inst9\|lpm_rom:inst\|otri\[0\] " "Warning: Converting TRI node \"urom:inst9\|lpm_rom:inst\|otri\[0\]\" that feeds logic to a wire" {  } { { "LPM_ROM.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/LPM_ROM.tdf" 64 6 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "60 " "Info: Ignored 60 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "60 " "Info: Ignored 60 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "inst15~4 " "Warning: Removed always-enabled tri-state buffer inst15~4 feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_OPT_REMOVED_ALWAYS_ENABLED_TRI" "inst16~4 " "Warning: Removed always-enabled tri-state buffer inst16~4 feeding logic, open-drain buffer or output pin" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "iopr:inst10\|74244:inst\|1~0 " "Warning: Converting TRI node \"iopr:inst10\|74244:inst\|1~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "mem:inst3\|74244:inst6\|1~0 " "Warning: Converting TRI node \"mem:inst3\|74244:inst6\|1~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "mem:inst3\|74244:inst6\|26~0 " "Warning: Converting TRI node \"mem:inst3\|74244:inst6\|26~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "iopr:inst10\|74244:inst\|6~0 " "Warning: Converting TRI node \"iopr:inst10\|74244:inst\|6~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "iopr:inst10\|74244:inst\|10~0 " "Warning: Converting TRI node \"iopr:inst10\|74244:inst\|10~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "iopr:inst10\|74244:inst\|11~0 " "Warning: Converting TRI node \"iopr:inst10\|74244:inst\|11~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "iopr:inst10\|74244:inst\|36~0 " "Warning: Converting TRI node \"iopr:inst10\|74244:inst\|36~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "iopr:inst10\|74244:inst\|31~0 " "Warning: Converting TRI node \"iopr:inst10\|74244:inst\|31~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "iopr:inst10\|74244:inst\|27~0 " "Warning: Converting TRI node \"iopr:inst10\|74244:inst\|27~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "iopr:inst10\|74244:inst\|26~0 " "Warning: Converting TRI node \"iopr:inst10\|74244:inst\|26~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "mem:inst3\|74244:inst6\|6~0 " "Warning: Converting TRI node \"mem:inst3\|74244:inst6\|6~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "mem:inst3\|74244:inst6\|10~0 " "Warning: Converting TRI node \"mem:inst3\|74244:inst6\|10~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "mem:inst3\|74244:inst6\|11~0 " "Warning: Converting TRI node \"mem:inst3\|74244:inst6\|11~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "mem:inst3\|74244:inst6\|36~0 " "Warning: Converting TRI node \"mem:inst3\|74244:inst6\|36~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "mem:inst3\|74244:inst6\|31~0 " "Warning: Converting TRI node \"mem:inst3\|74244:inst6\|31~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "mem:inst3\|74244:inst6\|27~0 " "Warning: Converting TRI node \"mem:inst3\|74244:inst6\|27~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "inst15~0 " "Warning: Converting TRI node \"inst15~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR" "inst16~0 " "Warning: Converting TRI node \"inst16~0\" that feeds logic to an OR gate" {  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "667 " "Info: Implemented 667 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "92 " "Info: Implemented 92 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "519 " "Info: Implemented 519 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "55 " "Info: Implemented 55 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 80 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 80 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 15 17:35:00 2008 " "Info: Processing ended: Tue Jan 15 17:35:00 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0}  } {  } 0}