iolpc2458.h

嵌入式的tcpip协议栈

#define U1IIR      U1FCR

__IO_REG8(U1LCR,0xE001000C,__READ_WRITE);
__IO_REG8(U1MCR,0xE0010010,__READ_WRITE);
__IO_REG8(U1LSR,0xE0010014,__READ);
__IO_REG8(U1MSR,0xE0010018,__READ);
__IO_REG8(U1SCR,0xE001001C,__READ_WRITE);
__IO_REG32(U1ACR,0xE0010020,__READ_WRITE);
__IO_REG32(U1FDR,0xE0010028,__READ_WRITE);
__IO_REG8(U1TER,0xE0010030,__READ_WRITE);

/***************************************************************************
 **
 **  UART2
 **
 ***************************************************************************/
/* U2DLL,U2RBR and U2THR share the same address */
__IO_REG8(U2RBRTHR,0xE0078000,__READ_WRITE);
#define U2DLL U2RBRTHR
#define U2RBR U2RBRTHR
#define U2THR U2RBRTHR

/* U2DLM and U2IER share the same address */
__IO_REG32(U2IER,0xE0078004,__READ_WRITE);
#define U2DLM      U2IER

/* U2FCR and U2IIR share the same address */
__IO_REG32(U2FCR,0xE0078008,__READ_WRITE);
#define U2IIR      U2FCR

__IO_REG8(U2LCR,0xE007800C,__READ_WRITE);
__IO_REG8(U2LSR,0xE0078014,__READ);
__IO_REG8(U2SCR,0xE007801C,__READ_WRITE);
__IO_REG32(U2ACR,0xE0078020,__READ_WRITE);
__IO_REG32(U2FDR,0xE0078028,__READ_WRITE);
__IO_REG8(U2TER,0xE0078030,__READ_WRITE);

/***************************************************************************
 **
 **  UART3
 **
 ***************************************************************************/
/* U3DLL,U3RBR and U3THR share the same address */
__IO_REG8(U3RBRTHR,0xE007C000,__READ_WRITE);
#define U3DLL U3RBRTHR
#define U3RBR U3RBRTHR
#define U3THR U3RBRTHR

/* U3DLM and U3IER share the same address */
__IO_REG32(U3IER,0xE007C004,__READ_WRITE);
#define U3DLM      U3IER

/* U3FCR and U3IIR share the same address */
__IO_REG32(U3FCR,0xE007C008,__READ_WRITE);
#define U3IIR      U3FCR

__IO_REG8(U3LCR,0xE007C00C,__READ_WRITE);
__IO_REG8(U3LSR,0xE007C014,__READ);
__IO_REG8(U3SCR,0xE007C01C,__READ_WRITE);
__IO_REG32(U3ACR,0xE007C020,__READ_WRITE);
__IO_REG32(U3ICR,0xE007C024,__READ_WRITE);
__IO_REG32(U3FDR,0xE007C028,__READ_WRITE);
__IO_REG8(U3TER,0xE007C030,__READ_WRITE);

/***************************************************************************
 **
 ** SPI
 **
 ***************************************************************************/
__IO_REG32(S0SPCR,0xE0020000,__READ_WRITE);
__IO_REG32(S0SPSR,0xE0020004,__READ);
__IO_REG16(S0SPDR,0xE0020008,__READ_WRITE);
__IO_REG32(S0SPCCR,0xE002000C,__READ_WRITE);
__IO_REG8(SPTCR,0xE0020010,__READ_WRITE);
__IO_REG8(SPTSR,0xE0020014,__READ_WRITE);
__IO_REG32(S0SPINT,0xE002001C,__READ_WRITE);

/***************************************************************************
 **
 ** SSP0
 **
 ***************************************************************************/
__IO_REG32(SSP0CR0,0xE0068000,__READ_WRITE);
__IO_REG32(SSP0CR1,0xE0068004,__READ_WRITE);
__IO_REG32(SSP0DR,0xE0068008,__READ_WRITE);
__IO_REG32(SSP0SR,0xE006800C,__READ);
__IO_REG32(SSP0CPSR,0xE0068010,__READ_WRITE);
__IO_REG32(SSP0IMSC,0xE0068014,__READ_WRITE);
__IO_REG32(SSP0RIS,0xE0068018,__READ_WRITE);
__IO_REG32(SSP0MIS,0xE006801C,__READ_WRITE);
__IO_REG32(SSP0ICR,0xE0068020,__READ_WRITE);
__IO_REG32(SSP0DMACR,0xE0068024,__READ_WRITE);

/***************************************************************************
 **
 ** SSP1
 **
 ***************************************************************************/
__IO_REG32(SSP1CR0,0xE0030000,__READ_WRITE);
__IO_REG32(SSP1CR1,0xE0030004,__READ_WRITE);
__IO_REG32(SSP1DR,0xE0030008,__READ_WRITE);
__IO_REG32(SSP1SR,0xE003000C,__READ);
__IO_REG32(SSP1CPSR,0xE0030010,__READ_WRITE);
__IO_REG32(SSP1IMSC,0xE0030014,__READ_WRITE);
__IO_REG32(SSP1RIS,0xE0030018,__READ_WRITE);
__IO_REG32(SSP1MIS,0xE003001C,__READ_WRITE);
__IO_REG32(SSP1ICR,0xE0030020,__READ_WRITE);
__IO_REG32(SSP1DMACR,0xE0030024,__READ_WRITE);

/***************************************************************************
 **
 ** SD/MMC
 **
 ***************************************************************************/
__IO_REG32(MCIPOWER,0xE008C000,__READ_WRITE);
__IO_REG32(MCICLOCK,0xE008C004,__READ_WRITE);
__IO_REG32(MCIARGUMENT,0xE008C008,__READ_WRITE);
__IO_REG32(MCICOMMAND,0xE008C00C,__READ_WRITE);
__IO_REG32(MCIRESPCMD,0xE008C010,__READ);
__IO_REG32(MCIRESPONSE0,0xE008C014,__READ);
__IO_REG32(MCIRESPONSE1,0xE008C018,__READ);
__IO_REG32(MCIRESPONSE2,0xE008C01C,__READ);
__IO_REG32(MCIRESPONSE3,0xE008C020,__READ);
__IO_REG32(MCIDATATIMER,0xE008C024,__READ_WRITE);
__IO_REG16(MCIDATALENGTH,0xE008C028,__READ_WRITE);
__IO_REG32(MCIDATACTRL,0xE008C02C,__READ_WRITE);
__IO_REG16(MCIDATACNT,0xE008C030,__READ);
__IO_REG32(MCISTATUS,0xE008C034,__READ);
__IO_REG32(MCICLEAR,0xE008C038,__WRITE);
__IO_REG32(MCIMASK0,0xE008C03C,__READ_WRITE);
__IO_REG32(MCIMASK1,0xE008C040,__READ_WRITE);
__IO_REG32(MCIFIFOCNT,0xE008C048,__READ);
__IO_REG32(MCIFIFO0,0xE008C080,__READ_WRITE);
__IO_REG32(MCIFIFO1,0xE008C084,__READ_WRITE);
__IO_REG32(MCIFIFO2,0xE008C088,__READ_WRITE);
__IO_REG32(MCIFIFO3,0xE008C08C,__READ_WRITE);
__IO_REG32(MCIFIFO4,0xE008C090,__READ_WRITE);
__IO_REG32(MCIFIFO5,0xE008C094,__READ_WRITE);
__IO_REG32(MCIFIFO6,0xE008C098,__READ_WRITE);
__IO_REG32(MCIFIFO7,0xE008C09C,__READ_WRITE);
__IO_REG32(MCIFIFO8,0xE008C0A0,__READ_WRITE);
__IO_REG32(MCIFIFO9,0xE008C0A4,__READ_WRITE);
__IO_REG32(MCIFIFO10,0xE008C0A8,__READ_WRITE);
__IO_REG32(MCIFIFO11,0xE008C0AC,__READ_WRITE);
__IO_REG32(MCIFIFO12,0xE008C0B0,__READ_WRITE);
__IO_REG32(MCIFIFO13,0xE008C0B4,__READ_WRITE);
__IO_REG32(MCIFIFO14,0xE008C0B8,__READ_WRITE);
__IO_REG32(MCIFIFO15,0xE008C0BC,__READ_WRITE);

/***************************************************************************
 **
 ** I2C0
 **
 ***************************************************************************/
__IO_REG32(I2C0CONSET,0xE001C000,__READ_WRITE);
__IO_REG32(I2C0STAT,0xE001C004,__READ);
__IO_REG32(I2C0DAT,0xE001C008,__READ_WRITE);
__IO_REG32(I2C0ADR,0xE001C00C,__READ_WRITE);
__IO_REG32(I2C0SCLH,0xE001C010,__READ_WRITE);
__IO_REG32(I2C0SCLL,0xE001C014,__READ_WRITE);
__IO_REG32(I2C0CONCLR,0xE001C018,__WRITE);

//The names of the registers above have been corrected according to the chip
//documentation. The defines below are aliases with the old names for backwards
//compatibility.
#define I20CONSET I2C0CONSET
#define I20STAT   I2C0STAT
#define I20DAT    I2C0DAT
#define I20ADR    I2C0ADR
#define I20SCLH   I2C0SCLH
#define I20SCLL   I2C0SCLL
#define I20CONCLR I2C0CONCLR

/***************************************************************************
 **
 ** I2C1
 **
 ***************************************************************************/
__IO_REG32(I2C1CONSET,0xE005C000,__READ_WRITE);
__IO_REG32(I2C1STAT,0xE005C004,__READ);
__IO_REG32(I2C1DAT,0xE005C008,__READ_WRITE);
__IO_REG32(I2C1ADR,0xE005C00C,__READ_WRITE);
__IO_REG32(I2C1SCLH,0xE005C010,__READ_WRITE);
__IO_REG32(I2C1SCLL,0xE005C014,__READ_WRITE);
__IO_REG32(I2C1CONCLR,0xE005C018,__WRITE);

//The names of the registers above have been corrected according to the chip
//documentation. The defines below are aliases with the old names for backwards
//compatibility.
#define I21CONSET I2C1CONSET
#define I21STAT   I2C1STAT
#define I21DAT    I2C1DAT
#define I21ADR    I2C1ADR
#define I21SCLH   I2C1SCLH
#define I21SCLL   I2C1SCLL
#define I21CONCLR I2C1CONCLR

/***************************************************************************
 **
 ** I2C2
 **
 ***************************************************************************/
__IO_REG32(I2C2CONSET,0xE0080000,__READ_WRITE);
__IO_REG32(I2C2STAT,0xE0080004,__READ);
__IO_REG32(I2C2DAT,0xE0080008,__READ_WRITE);
__IO_REG32(I2C2ADR,0xE008000C,__READ_WRITE);
__IO_REG32(I2C2SCLH,0xE0080010,__READ_WRITE);
__IO_REG32(I2C2SCLL,0xE0080014,__READ_WRITE);
__IO_REG32(I2C2CONCLR,0xE0080018,__WRITE);

/***************************************************************************
 **
 ** I2S
 **
 ***************************************************************************/
__IO_REG32(I2SDAO,0xE0088000,__READ_WRITE);
__IO_REG32(I2SDAI,0xE0088004,__READ_WRITE);
__IO_REG32(I2STXFIFO,0xE0088008,__WRITE);
__IO_REG32(I2SRXFIFO,0xE008800C,__READ);
__IO_REG32(I2SSTATE,0xE0088010,__READ);
__IO_REG32(I2SDMA1,0xE0088014,__READ_WRITE);
__IO_REG32(I2SDMA2,0xE0088018,__READ_WRITE);
__IO_REG32(I2SIRQ,0xE008801C,__READ_WRITE);
__IO_REG32(I2STXRATE,0xE0088020,__READ_WRITE);
__IO_REG32(I2SRXRATE,0xE0088024,__READ_WRITE);

/***************************************************************************
 **
 ** TIMER0
 **
 ***************************************************************************/
__IO_REG32(T0IR,0xE0004000,__READ_WRITE);
__IO_REG32(T0TCR,0xE0004004,__READ_WRITE);
__IO_REG32(T0TC,0xE0004008,__READ_WRITE);
__IO_REG32(T0PR,0xE000400C,__READ_WRITE);
__IO_REG32(T0PC,0xE0004010,__READ_WRITE);
__IO_REG32(T0MCR,0xE0004014,__READ_WRITE);
__IO_REG32(T0MR0,0xE0004018,__READ_WRITE);
__IO_REG32(T0MR1,0xE000401C,__READ_WRITE);
__IO_REG32(T0MR2,0xE0004020,__READ_WRITE);
__IO_REG32(T0MR3,0xE0004024,__READ_WRITE);
__IO_REG32(T0CCR,0xE0004028,__READ_WRITE);
__IO_REG32(T0CR0,0xE000402C,__READ);
__IO_REG32(T0CR1,0xE0004030,__READ);
__IO_REG32(T0CR2,0xE0004034,__READ);
__IO_REG32(T0CR3,0xE0004038,__READ);
__IO_REG32(T0EMR,0xE000403C,__READ_WRITE);
__IO_REG32(T0CTCR,0xE0004070,__READ_WRITE);

/***************************************************************************
 **
 ** TIMER1
 **
 ***************************************************************************/
__IO_REG32(T1IR,0xE0008000,__READ_WRITE);
__IO_REG32(T1TCR,0xE0008004,__READ_WRITE);
__IO_REG32(T1TC,0xE0008008,__READ_WRITE);
__IO_REG32(T1PR,0xE000800C,__READ_WRITE);
__IO_REG32(T1PC,0xE0008010,__READ_WRITE);
__IO_REG32(T1MCR,0xE0008014,__READ_WRITE);
__IO_REG32(T1MR0,0xE0008018,__READ_WRITE);
__IO_REG32(T1MR1,0xE000801C,__READ_WRITE);
__IO_REG32(T1MR2,0xE0008020,__READ_WRITE);
__IO_REG32(T1MR3,0xE0008024,__READ_WRITE);
__IO_REG32(T1CCR,0xE0008028,__READ_WRITE);
__IO_REG32(T1CR0,0xE000802C,__READ);
__IO_REG32(T1CR1,0xE0008030,__READ);
__IO_REG32(T1CR2,0xE0008034,__READ);
__IO_REG32(T1CR3,0xE0008038,__READ);
__IO_REG32(T1EMR,0xE000803C,__READ_WRITE);
__IO_REG32(T1CTCR,0xE0008070,__READ_WRITE);

/***************************************************************************
 **