core.h

ucos 在arca方舟芯片（mips）上的移植。

//=============================================================================
//
//      hal_regs.h
// Purpose:     Define CPU memory mapped registers etc.
//              
//=============================================================================

//--------------------------------------------------------------------------
/* Status register */
#define UCOS_REG_SR_IE           0x01 /* Interrupt enable */
#define UCOS_REG_SR_DE           0x02 /* Debug enable */ 
#define UCOS_REG_SR_DS           0x04 /* Debug state */
#define UCOS_REG_SR_SM           0x08 /* Supervisor mode */
#define UCOS_REG_SR_VB           0x70 /* Vector base */

//--------------------------------------------------------------------------
// Cache registers
#define UCOS_REG_CCR              0x5   /* ID=0 CR=5 */

#define UCOS_REG_CCR_P0B         0x01   /* */
#define UCOS_REG_CCR_P1B         0x02   /* */
#define UCOS_REG_CCR_P2B         0x04   /* */
#define UCOS_REG_CCR_P3B         0x08   /* */
#define UCOS_REG_CCR_P3C         0x10   /* */
#define UCOS_REG_CCR_DCE         0x20   /* D-cache enable */
#define UCOS_REG_CCR_ICE         0x40   /* I-cache enable */


//--------------------------------------------------------------------------
// MMU control registers
#define UCOS_REG_MMUCR           0		/* Initial Value 0x00000000 */

#define UCOS_REG_MMUCR_ATE       0x0001	/* Addr translation en/dis */
#define UCOS_REG_MMUCR_IX        0x0002	/* DTLB and ITLB entr index
						 * mode bit */
#define UCOS_REG_MMUCR_ITI       0x0004	/* ITLB invalid bit */
#define UCOS_REG_MMUCR_DTI       0x0008	/* DTLB invalid bit */
#define UCOS_REG_MMUCR_SV        0x0010	/* Single virt memory mode */
#define UCOS_REG_MMUCR_DRC       0x0300	/* A 2bit random cnt of
						 * the DTLB repl */
#define UCOS_REG_MMUCR_IRC       0x0C00	/* A 2bit random cnt of the
						 * ITLB repl */

 /* UCOS ONCE_PLF_INTR_H */
#define UCOS_NUM_HAL_VSR_EXCEPTION_COUNT             8
#define UCOS_NUM_HAL_RTC_PERIOD                100
#define UCOS_NUM_HAL_VECTORESET                    0 // reset
#define UCOS_NUM_HAL_VECTOR_ILLEGAL_INSTRUCTION      1 // reserved instruction
#define UCOS_NUM_HAL_VECTOR_DEBUG                    2 // debug
#define UCOS_NUM_HAL_VECTOR_RESERVE1                 3 
#define UCOS_NUM_HAL_VECTOR_INTERRUPT                4 // all interrupt base
#define UCOS_NUM_HAL_VECTOR_TRAP                     5
#define UCOS_NUM_HAL_VECTOR_FAULT                    6
#define UCOS_NUM_HAL_VECTOR_RESERVE2                 7


#if !defined(__ASSEMBLY__)

typedef struct {
    unsigned int r[32];
    unsigned int sr;
    unsigned int pc;
} HAL_SavedRegisters;

#endif