hal_regs.h

ucos 在arca方舟芯片（mips）上的移植。

/*TER  ******************/
#define UCOS_REG_TER			0xE0000200  /* Init Val 0x00 R/W */
#define UCOS_REG_TER_TE0		0x01	/* Starts channel 0 count */
#define UCOS_REG_TER_TE1		0x02    /* Starts channel 1 count */
#define UCOS_REG_TER_TE2		0x04    /* Starts channel 2 count */

// CGU Control registers
#define UCOS_REG_CGU_CFCR        0xE0000100
#define UCOS_REG_CGU_PLCR1       0xE0000110
#define UCOS_REG_CGU_PLCR2       0xE0000114
/*  CYGONCE_HAL_CGU_REG_H  */

// TCSR
#define UCOS_REG_TCSR_CKS_F4		0x0000  /* Internal clock: f/4 */
#define UCOS_REG_TCSR_CKS_F16		0x0001  /* Internal clock: f/16 */
#define UCOS_REG_TCSR_CKS_F64		0x0002  /* Internal clock: f/64 */
#define UCOS_REG_TCSR_CKS_256		0x0003  /* Internal clock: f/256 */
#define UCOS_REG_TCSR_CKS_RTCCLK	0x0004  /* Internal clock: RTC output
						 * clock (RTCCLK) */
#define UCOS_REG_TCSR_CKS_TCLK	0x0005  /* Reserved */
#define UCOS_REG_TCSR_CKS_RSV6	0x0006  /* Reserved */
#define UCOS_REG_TCSR_CKS_RSV7	0x0007  /* Reserved */

#define UCOS_REG_TCSR_UIE		0x0020  /* Underflow intr is enabled */
#define UCOS_REG_TCSR_UF		0x0040  /* TCNT underflow occurred */

// Only chanel 2 can set these values
#define UCOS_REG_TCSR_ECE		0x0080  /* Event capture function
						 * is enabled */
#define UCOS_REG_TCSR_ECIE		0x0100  /* Int due to event capture
						 * is enabled */
#define UCOS_REG_TCSR_ECF		0x0200  /* Event capture occurred */

// TMU registers
#define UCOS_REG_TER			0xE0000200  /* Init Val 0x00 R/W */
#define UCOS_REG_TRDR0		0xE0000204  /* Init Val 0xFFFFFFFF */
#define UCOS_REG_TCNT0		0xE0000208  /* Init Val 0xFFFFFFFF */
#define UCOS_REG_TCSR0		0xE000020C  /* Init Val 0x0000 */
#define UCOS_REG_TRDR1		0xE0000210  /* Init Val 0xFFFFFFFF */
#define UCOS_REG_TCNT1		0xE0000214  /* Init Val 0xFFFFFFFF */
#define UCOS_REG_TCSR1		0xE0000218  /* Init Val 0x0000 */
#define UCOS_REG_TRDR2		0xE000021C  /* Init Val 0xFFFFFFFF */
#define UCOS_REG_TCNT2		0xE0000220  /* Init Val 0xFFFFFFFF */
#define UCOS_REG_TCSR2		0xE0000224  /* Init Val 0x0000 */

//  GPIO registers
#define UCOS_REG_GPCR_A          0xE0000500  /* GPIO control register.
						* RW 32-bit 0x00000000 */
#define UCOS_REG_GPDR_A          0xE0000504  /* GPIO data register. 
						* RW 8-bit */
#define UCOS_REG_GPCR_B          0xE0000510  /* R/W 32-bit */
#define UCOS_REG_GPDR_B          0xE0000514  /* R/W 8-bit */ 
#define UCOS_REG_GPETR_B         0xE0000518  /* R/W 16-bit */
#define UCOS_REG_GPFR_B          0xE000051c  /* R/W 8-bit */
#define UCOS_REG_GPCR_C          0xE0000520  /* R/W 32-bit */
#define UCOS_REG_GPDR_C          0xE0000524  /* R/W 8-bit */ 
#define UCOS_REG_GPCR_D          0xE0000530  /* R/W 32-bit */
#define UCOS_REG_GPDR_D          0xE0000534  /* R/W 8-bit */ 
#define UCOS_REG_GPCR_E          0xE0000540  /* R/W 32-bit */
#define UCOS_REG_GPDR_E          0xE0000544  /* R/W 8-bit */ 
#define UCOS_REG_GPCR_F          0xE0000550  /* R/W 32-bit */
#define UCOS_REG_GPDR_F          0xE0000554  /* R/W 8-bit */ 

/*  CYGONCE_HAL_GPIO_REG_H  */
#define UCOS_REG_IMCR		0xE000000C	/* Intr mask clear reg. 32b */
#define UCOS_REG_IMSR		0xE0000008	/* Intr mask set reg. 32b */
#define UCOS_REG_IPR		0xE0000010	/* Intr pending reg. 32b */