hal_dma.h

ucos 在arca方舟芯片（mips）上的移植。

#ifndef CYGONCE_HAL_DMA_REG_H
#define CYGONCE_HAL_DMA_REG_H

#define DMAC_BASE           0xE1030000

#define DMAC_DSAR0	(DMAC_BASE + 0x00)   /* 32-bit RW H'00000000 */
#define DMAC_DDAR0	(DMAC_BASE + 0x04)   /* 32-bit RW H'00000000 */
#define DMAC_DCTR0	(DMAC_BASE + 0x08)   /* 32-bit RW H'00000000 */
#define DMAC_DCCSR0	(DMAC_BASE + 0x0C)   /* 32-bit RW H'00000000 */
#define DMAC_DCCSR1	(DMAC_BASE + 0x1C)   /* 32-bit RW H'00000000 */
#define DMAC_DCCSR2	(DMAC_BASE + 0x2C)   /* 32-bit RW H'00000000 */
#define DMAC_DSAR3	(DMAC_BASE + 0x30)   /* 32-bit RW H'00000000 */
#define DMAC_DDAR3	(DMAC_BASE + 0x34)   /* 32-bit RW H'00000000 */
#define DMAC_DCTR3	(DMAC_BASE + 0x38)   /* 32-bit RW H'00000000 */
#define DMAC_DCCSR3	(DMAC_BASE + 0x3C)   /* 32-bit RW H'00000000 */
#define DMAC_DMACR	(DMAC_BASE + 0x40)   /* 32-bit RW H'00000000 */

/*
 * Define macros for DMAC.DMACR
 * DMA Control Register
 */
#define DMAC_DISABLE         0
#define DMAC_ENABLE          (1 <<0 )
#define DMAC_PRIORITY_0123   (0 << 8)
#define DMAC_PRIORITY_0231   (1 << 8)
#define DMAC_PRIORITY_2013   (2 << 8)
#define DMAC_PRIORITY_RR     (3 << 8)
#define DMAC_ADDR_ERR_FLAG   (1<<2)

/*
 * Define macros for DMAC.DCCSRn
 * DMA Channel Control/Status Register n
 */
#define DMAC_CH_DISABLE         0
#define DMAC_CH_ENABLE          (1 << 0)
#define DMAC_CH_INTR_DISABLE    0
#define DMAC_CH_INTR_ENABLE     (1 << 1)
#define DMAC_CH_TRANS_END_FLAG  (1 << 3)
#define DMAC_CH_ADDR_ERR_FLAG   (1 << 4)

#define DMAC_DISCONTIG_TRANS_MODE  0
#define DMAC_CONTIG_TRANS_MODE     (1 << 5)
#define DMAC_SINGLE_MODE           0
#define DMAC_BLOCK_MODE            (1 << 7)

#define DMAC_EXTERNAL_REQ_MODE   (0x00 << 8)
#define DMAC_PCMCIA0_READ_MODE   (0x04 << 8)
#define DMAC_PCMCIA0_WRITE_MODE  (0x05 << 8)
#define DMAC_PCMCIA1_READ_MODE   (0x06 << 8)
#define DMAC_PCMCIA1_WRITe_MODE  (0x07 << 8)
#define DMAC_AUTO_REQ_MODE       (0x08 << 8)
#define DMAC_UART_WRITE_MODE     (0x10 << 8)
#define DMAC_UART_READ_MODE      (0x11 << 8)
#define DMAC_IrDA_WRITE_MODE     (0x12 << 8)
#define DMAC_IrDA_READ_MODE      (0x13 << 8)
#define DMAC_AC97_WRITE_MODE     (0x14 << 8)
#define DMAC_AC97_READ_MODE      (0x15 << 8)
#define DMAC_TMU2_REQ_MODE       (0x1C << 8)

#define DMAC_ADDR_MODE_MASK      0x4000C000
#define DMAC_DA_FIXED_MODE       (0x00 << 14)
#define DMAC_DA_INC_MODE         (0x01 << 14)
#define DMAC_SA_FIXED_MODE       (0x00 << 15)
#define DMAC_SA_INC_MODE         (0x01 << 15)
#define DACK_IN_READ_CYC         (0x00 << 30)
#define DACK_IN_WRITE_CYC        (0x01 << 30)

#define DMAC_TRANS_UNIT_32bit    (0x00 << 21)
#define DMAC_TRANS_UNIT_8bit     (0x01 << 21)
#define DMAC_TRANS_UNIT_16bit    (0x02 << 21)
#define DMAC_TRANS_UNIT_16byte   (0x03 << 21)
#define DMAC_TRANS_UNIT_32byte   (0x04 << 21)

#define DMAC_RDIL_IGNORED        (0x00 << 16)
#define DMAC_RDIL_2UNIT          (0x01 << 16)
#define DMAC_RDIL_3UNIT          (0x02 << 16)
#define DMAC_RDIL_4UNIT          (0x03 << 16)
#define DMAC_RDIL_5UNIT          (0x04 << 16)
#define DMAC_RDIL_6UNIT          (0x05 << 16)
#define DMAC_RDIL_7UNIT          (0x06 << 16)
#define DMAC_RDIL_8UNIT          (0x07 << 16)
#define DMAC_RDIL_9UNIT          (0x08 << 16)
#define DMAC_RDIL_10UNIT         (0x09 << 16)
#define DMAC_RDIL_11UNIT         (0x0a << 16)
#define DMAC_RDIL_12UNIT         (0x0b << 16)
#define DMAC_RDIL_13UNIT         (0x0c << 16)
#define DMAC_RDIL_14UNIT         (0x0d << 16)
#define DMAC_RDIL_15UNIT         (0x0e << 16)
#define DMAC_RDIL_16UNIT         (0x0f << 16)

#define EOP_HIGH_LEVEL           (0 << 27)
#define EOP_LOW_LEVEL            (1 << 27)
#define EREQ_LOW_LEVEL           (0 << 28)
#define EREQ_FALL_EDGE           (1 << 28)
#define EREQ_HIGH_LEVEL          (2 << 28)
#define EREQ_RISE_EDGE           (3 << 28)
#define EACK_HIGH_LEVEL          (0 << 31)
#define EACK_LOW_LEVEL           (1 << 31)


#endif /*  CYGONCE_HAL_DMA_REG_H  */