hal_regs.h

ucos 在arca方舟芯片（mips）上的移植。

//--------------------------------------------------------------------------
// TMU registers
#define UCOS_REG_TER			0xE0000200  /* Init Val 0x00 R/W */
#define UCOS_REG_TRDR0		0xE0000204  /* Init Val 0xFFFFFFFF */
#define UCOS_REG_TCNT0		0xE0000208  /* Init Val 0xFFFFFFFF */
#define UCOS_REG_TCSR0		0xE000020C  /* Init Val 0x0000 */
#define UCOS_REG_TRDR1		0xE0000210  /* Init Val 0xFFFFFFFF */
#define UCOS_REG_TCNT1		0xE0000214  /* Init Val 0xFFFFFFFF */
#define UCOS_REG_TCSR1		0xE0000218  /* Init Val 0x0000 */
#define UCOS_REG_TRDR2		0xE000021C  /* Init Val 0xFFFFFFFF */
#define UCOS_REG_TCNT2		0xE0000220  /* Init Val 0xFFFFFFFF */
#define UCOS_REG_TCSR2		0xE0000224  /* Init Val 0x0000 */

// TER
#define UCOS_REG_TER_TE0		0x01	/* Starts channel 0 count */
#define UCOS_REG_TER_TE1		0x02    /* Starts channel 1 count */
#define UCOS_REG_TER_TE2		0x04    /* Starts channel 2 count */

// TCSR
#define UCOS_REG_TCSR_CKS_F4		0x0000  /* Internal clock: f/4 */
#define UCOS_REG_TCSR_CKS_F16		0x0001  /* Internal clock: f/16 */
#define UCOS_REG_TCSR_CKS_F64		0x0002  /* Internal clock: f/64 */
#define UCOS_REG_TCSR_CKS_256		0x0003  /* Internal clock: f/256 */
#define UCOS_REG_TCSR_CKS_RTCCLK	0x0004  /* Internal clock: RTC output
						 * clock (RTCCLK) */
#define UCOS_REG_TCSR_CKS_TCLK	0x0005  /* Reserved */
#define UCOS_REG_TCSR_CKS_RSV6	0x0006  /* Reserved */
#define UCOS_REG_TCSR_CKS_RSV7	0x0007  /* Reserved */

#define UCOS_REG_TCSR_UIE		0x0020  /* Underflow intr is enabled */
#define UCOS_REG_TCSR_UF		0x0040  /* TCNT underflow occurred */

// Only chanel 2 can set these values
#define UCOS_REG_TCSR_ECE		0x0080  /* Event capture function
						 * is enabled */
#define UCOS_REG_TCSR_ECIE		0x0100  /* Int due to event capture
						 * is enabled */
#define UCOS_REG_TCSR_ECF		0x0200  /* Event capture occurred */

// CGU Control registers
#define UCOS_REG_CGU_CFCR        0xE0000100
#define UCOS_REG_CGU_LPCR        0xE0000104
#define UCOS_REG_CGU_RSTR        0xE0000108

// CFCR bit define
#define UCOS_REG_CGU_CFCR_PLLEN  (1<<10) 
#define UCOS_REG_CGU_CFCR_DFR    (3<<6)  
#define UCOS_REG_CGU_CFCR_BFR    (3<<3)  
#define UCOS_REG_CGU_CFCR_IFR    (3<<0)

#define UCOS_REG_CGU_MODE_0_CFCR 0x0400 /* MD_clk2-0: 000; i:b:d=1:1:1 */
#define UCOS_REG_CGU_MODE_1_CFCR 0x0448 /* MD_clk2-0: 001; i:b:d=1:1/2:1/2 */
#define UCOS_REG_CGU_MODE_2_CFCR 0x0490 /* MD_clk2-0: 010; i:b:d=1:1/3:1/3 */
#define UCOS_REG_CGU_MODE_3_CFCR 0x04d8 /* MD_clk2-0: 011; i:b:d=1:1/4:1/4 */
#define UCOS_REG_CGU_MODE_4_CFCR 0x0    /* MD_clk2-0: 100; i:b:d=1:1:1 */

//--------------------------------------------------------------------------
//  GPIO registers
#define UCOS_REG_GPCR_A          0xE0000500  /* GPIO control register.
						* RW 32-bit 0x00000000 */
#define UCOS_REG_GPDR_A          0xE0000504  /* GPIO data register. 
						* RW 8-bit */
#define UCOS_REG_GPCR_B          0xE0000510  /* R/W 32-bit */
#define UCOS_REG_GPDR_B          0xE0000514  /* R/W 8-bit */ 
#define UCOS_REG_GPETR_B         0xE0000518  /* R/W 16-bit */
#define UCOS_REG_GPFR_B          0xE000051c  /* R/W 8-bit */
#define UCOS_REG_GPCR_C          0xE0000520  /* R/W 32-bit */
#define UCOS_REG_GPDR_C          0xE0000524  /* R/W 8-bit */ 
#define UCOS_REG_GPCR_D          0xE0000530  /* R/W 32-bit */
#define UCOS_REG_GPDR_D          0xE0000534  /* R/W 8-bit */ 
#define UCOS_REG_GPCR_E          0xE0000540  /* R/W 32-bit */
#define UCOS_REG_GPDR_E          0xE0000544  /* R/W 8-bit */ 
#define UCOS_REG_GPCR_F          0xE0000550  /* R/W 32-bit */
#define UCOS_REG_GPDR_F          0xE0000554  /* R/W 8-bit */ 

#define __hal_gpio_ethc_enable()		\
do {						\
    REG32(UCOS_REG_GPCR_E) |= 0xF800;		\
    REG32(UCOS_REG_GPCR_F) |= 0xFF00;		\
} while (0)

/* PCIB control registers */
#define PCIB_IN_MAILBOX0	0xE1000000	/* PCIB in mailbox0 */
#define PCIB_IN_MAILBOX1	0xE1000004	/* PCIB in mailbox1 */
#define PCIB_IN_MAILBOX2	0xE1000008	/* PCIB in mailbox2 */
#define PCIB_IN_MAILBOX3	0xE100000C	/* PCIB in mailbox3 */
#define PCIB_OUT_MAILBOX0	0xE1000010	/* PCIB out mailbox0 */
#define PCIB_OUT_MAILBOX1	0xE1000014	/* PCIB out mailbox1 */
#define PCIB_OUT_MAILBOX2	0xE1000018	/* PCIB out mailbox2 */
#define PCIB_OUT_MAILBOX3	0xE100001C	/* PCIB out mailbox3 */
#define PCIB_MAIL_STATUS	0xE1000020	/* PCIB mail box status */
#define PCIB_PCIB_DOORBELL	0xE1000024	/* PCIB PCIB doorbell */
#define PCIB_PCI_DOORBELL	0xE1000028	/* PCIB PCI doorbell */
#define PCICFG_ADDR		0xE100002C	/* PCIB config address */
#define PCICFG_DATA		0xE1000030	/* PCIB config data */
#define PCIB_STATUS		0xE1000034	/* PCIB status */
#define PCIB_CONTROL		0xE1000038	/* PCIB control */
#define PCIB_SLVWIN		0xE1000040	/* PCIB slave window */
#define PCIB_PCIMEM0		0xE1000044	/* PCIB pcimem 0 */
#define PCIB_PCIMEM1		0xE1000048	/* PCIB pcimem 1 */
#define PCIB_PCIMEM2		0xE100004C	/* PCIB pcimem 2 */
#define PCIB_PCIIO		0xE1000050	/* PCIB pciio */
#define PCIC_INTACK		0xE1000054	/* PCIC int acknowlege */

/*
 * Define macros for PCIC.IER, PCIC Interrupt Enable Register.
 * And known as PCI_CONTROL register.
 */
#define	SATELLITE_MODE           0 
#define	HOST_MODE                (1 << 0)
#define	PCIC_INTR_DISABLE        0
#define	PCIC_INTR_ENABLE         (1 << 1)
#define	PCIC_MAIL_INTR_DISABLE   0
#define	PCIC_MAIL_INTR_ENABLE    (1 << 2)

/* PCIB Status Regs bit mask */
#define PCIB_INTA		(1 << 12)
#define PCIB_INTB		(1 << 13)
#define PCIB_INTC		(1 << 14)
#define PCIB_INTD		(1 << 15)

/* Arca PCI config area */
#define PCICFG_VENDOR_ID	0xE1000100
#define PCICFG_DEVICE_ID	0xE1000102
#define PCICFG_COMMAND		0xE1000104
#define PCICFG_STATUS		0xE1000106
#define PCICFG_REVISION_ID	0xE1000108
#define PCICFG_CLASSCODE	0xE1000109
#define PCICFG_CACHELINE_SIZE	0xE100010C
#define PCICFG_LATENCY_TIME	0xE100010D
#define PCICFG_HEADER_TYPE	0xE100010E
#define PCICFG_BIST		0xE100010F
#define PCICFG_MEM_BASE0	0xE1000110
#define PCICFG_MEM_BASE1	0xE1000114
#define PCICFG_INTR_LINE	0xE100013C
#define PCICFG_INTR_PIN		0xE100013D
#define PCICFG_MIN_GNT		0xE100013E
#define PCICFG_MAX_LAT		0xE100013F
#define PCICFG_TRDY_TIMER	0xE1000140
#define PCICFG_RETRY_TIMER	0xE1000141

// EMI registers
#define REG_EMI_BCR		0xE1020000
#define REG_EMI_SMCR0		0xE1020004
#define REG_EMI_SMCR1		0xE1020008
#define REG_EMI_SMCR2		0xE102000C
#define REG_EMI_SMCR3		0xE1020010
#define REG_EMI_DMCR		0xE1020014
#define REG_EMI_RTCSR		0xE1020018
#define REG_EMI_RTCNT		0xE102001C
#define REG_EMI_RTCOR		0xE1020020

#define REG_EMI_DMAR_BASE	0xE1020040
#define REG_EMI_DMAR_SIZE	0x4
#define REG_EMI_DMAR1		0xE1020040
#define REG_EMI_DMAR2		0xE1020044
#define REG_EMI_DMAR3		0xE1020048
#define REG_EMI_DMAR4		0xE102004C

#define REG_EMI_SDMR1_BASE	0xE102A000
#define REG_EMI_SDMR2_BASE	0xE102B000
#define REG_EMI_SDMR3_BASE	0xE102C000
#define REG_EMI_SDMR4_BASE	0xE102D000

#define EMI_BCR_HIZMEM		0x80
#define EMI_BCR_HIZCNT		0x40
#define EMI_BCR_ENDIAN		0x00
#define EMI_BCR_ENDIAN_BIG	0x00
#define EMI_BCR_ENDIAN_LITTLE	0x01

#define EMI_RTCSR_NINPUT	0x0
#define EMI_RTCSR_CKO_FIELD	0x7

#define EMI_SMCR_SMT_FIELD	0x1
#define EMI_SMCR_BL_FIELD	0x6
#define EMI_SMCR_BCM_FIELD	0x8
#define EMI_SMCR_BW_FIELD 	0xC0
#define EMI_SMCR_SPEED_FIELD	0x0FFF7700

#define EMI_DMCR_TYPE_FIELD	0x40000000
#define EMI_DMCR_PGM_FIELD	0x20000000
#define EMI_DMCR_CA_FIELD	0x1C000000
#define EMI_DMCR_RMODE_FIELD	0x02000000
#define EMI_DMCR_RFRH_FIELD	0x01000000
#define EMI_DMCR_MRSET_FIELD	0x00800000
#define EMI_DMCR_CS_FIELD	0x00400000
#define EMI_DMCR_RA_FIELD	0x00300000
#define EMI_DMCR_BA_FIELD	0x00080000
#define EMI_DMCR_PDM_FIELD	0x00040000
#define EMI_DMCR_TRAS_FIELD	0x0000E000
#define EMI_DMCR_RCD_FIELD	0x00001800
#define EMI_DMCR_TPC_FIELD	0x00000700
#define EMI_DMCR_TRWL_FIELD	0x00000060
#define EMI_DMCR_TRC_FIELD	0x0000001C
#define EMI_DMCR_TCL_FIELD	0x00000003
/* ---------------------------------------------------------- */
#define EMI_RTCOR_VAL        0x02    /* 64 * Nns < 1.6us (64: PCLK/64, N < 25) */
#define EMI_RTCNT_VAL        0x00

/* data[] offset define */
#define ROW              0
#define COL              1
#define CHIP             2   //CS
#define BANK             3
#define CAS_LATENCY      4
#define REFRESH_RATE     5 
#define RCD              6
#define TPC              7
#define TRWL             8
#define TRAS             9 
#define SIZE             10 
#define DENSITY          11   //is 0 when use hci and default.
#define DIMM             12   //maybe 0,1,2, is 0 when use hci and default.
#define SODIMM           13   //maybe 0,1

/* SDMR L define */
#define EMI_SDMR1_L2	        0xE102A088
#define EMI_SDMR2_L2	        0xE102B088
#define EMI_SDMR3_L2	        0xE102C088
#define EMI_SDMR4_L2	        0xE102D088

#define EMI_SDMR1_L3	        0xE102A0C8
#define EMI_SDMR2_L3	        0xE102B0C8
#define EMI_SDMR3_L3	        0xE102C0C8
#define EMI_SDMR4_L3	        0xE102D0C8

/* RTCSR CKO define */
#define EMI_RTCSR_CKO_F4		0x1
#define EMI_RTCSR_CKO_F16	0x2
#define EMI_RTCSR_CKO_F64	0x3
#define EMI_RTCSR_CKO_F256	0x4

#define EMI_SMCR_SPEED_FAST0	0x00000000 /* The fastest speed *//* To be fixed by precious value */
#define EMI_SMCR_SPEED_FAST1	0x03332200 /* STRV & TAW & TBP & TAH & TAS is 3 & 3 & 3 & 2 & 2 */
#define EMI_SMCR_SPEED_FAST2	0x05553300
#define EMI_SMCR_SPEED_NORM	0x0AAA7700
#define EMI_SMCR_SPEED_SLOW	0x0FFF7700

#define EMI_DMCR_TYPE_SODIMM   	0x40000000 /* The DRAM is SODIMM */

#define EMI_DMCR_RFRH_NFRH	0x00000000 /* No refresh is performed */
#define EMI_DMCR_RFRH_FRH	0x01000000 /* Refresh is performed */

#define EMI_DMCR_MRSET_PRECH	0x00000000 /* All bank is to precharge (by write the mode register */
#define EMI_DMCR_MRSET_MODSET	0x00800000 /* Mode register is to be set (by write the mode register */

#define EMI_DMCR_SPEED_SLOW	0x0000FFFD

// Interrupt controller registers
#define UCOS_REG_ISR		0xE0000000	/* Intr ctrl reg. 32b */
#define UCOS_REG_IMR		0xE0000004	/* Intr mask reg. 32b */
#define UCOS_REG_IMSR		0xE0000008	/* Intr mask set reg. 32b */
#define UCOS_REG_IMCR		0xE000000C	/* Intr mask clear reg. 32b */
#define UCOS_REG_IPR		0xE0000010	/* Intr pending reg. 32b */

// The decoded interrupts.
#define UCOS_NUM_HAL_INTERRUPT_I2CI       0x01
#define UCOS_NUM_HAL_INTERRUPT_AC97       0x03
#define UCOS_NUM_HAL_INTERRUPT_PMON       0x06
#define UCOS_NUM_HAL_INTERRUPT_SARB       0x07
#define UCOS_NUM_HAL_INTERRUPT_UART       0x08
#define UCOS_NUM_HAL_INTERRUPT_UART2      0x09
#define UCOS_NUM_HAL_INTERRUPT_IRDA       0x09
#define UCOS_NUM_HAL_INTERRUPT_UART2IRDA  0x09
#define UCOS_NUM_HAL_INTERRUPT_UHC        0x0d
#define UCOS_NUM_HAL_INTERRUPT_IRQ7       0x0e
#define UCOS_NUM_HAL_INTERRUPT_IRQ6       0x0f
#define UCOS_NUM_HAL_INTERRUPT_IRQ5       0x10
#define UCOS_NUM_HAL_INTERRUPT_IRQ4       0x11
#define UCOS_NUM_HAL_INTERRUPT_ETHC       0x13 
#define UCOS_NUM_HAL_INTERRUPT_PCI        0x14
#define UCOS_NUM_HAL_INTERRUPT_DMA        0x15
#define UCOS_NUM_HAL_INTERRUPT_RTCI       0x16
#define UCOS_NUM_HAL_INTERRUPT_TMU        0x17
#define UCOS_NUM_HAL_INTERRUPT_IRQ3       0x1a
#define UCOS_NUM_HAL_INTERRUPT_IRQ2       0x1b
#define UCOS_NUM_HAL_INTERRUPT_IRQ1       0x1c
#define UCOS_NUM_HAL_INTERRUPT_IRQ0       0x1d

#define UCOS_NUM_HAL_INTERRUPT_LAST       0x1f

#define UCOS_NUM_HAL_INTERRUPT_RTC        UCOS_NUM_HAL_INTERRUPT_TMU
// second level intr decode.
#define UCOS_NUM_HAL_INTERRUPT_PCI_DBELL  0x28
#define UCOS_NUM_HAL_INTERRUPT_PCI_INTA	0x29
#define UCOS_NUM_HAL_INTERRUPT_PCI_INTB	0x2a
#define UCOS_NUM_HAL_INTERRUPT_PCI_INTC	0x2b
#define UCOS_NUM_HAL_INTERRUPT_PCI_INTD	0x2c

#define UCOS_NUM_HAL_INTERRUPT_DMA_DEI0   0x24
#define UCOS_NUM_HAL_INTERRUPT_DMA_DEI1   0x25
#define UCOS_NUM_HAL_INTERRUPT_DMA_DEI2   0x26
#define UCOS_NUM_HAL_INTERRUPT_DMA_DEI3   0x27

#define UCOS_NUM_HAL_INTERRUPT_TMU0_TUNI0	0x20
#define UCOS_NUM_HAL_INTERRUPT_TMU1_TUNI1	0x21
#define UCOS_NUM_HAL_INTERRUPT_TMU2_TUNI2	0x22
#define UCOS_NUM_HAL_INTERRUPT_TMU2_TICPI	0x23

#define UCOS_NUM_HAL_INTERRUPT_unused     0xff

// UCOS_NUM_HAL_ISR_COUNT must match CYG_ISR_TABLE_SIZE defined in vectors.S.
#define UCOS_NUM_HAL_ISR_MIN    0x00
#define UCOS_NUM_HAL_ISR_MAX    0x2c
#define UCOS_NUM_HAL_ISR_COUNT (UCOS_NUM_HAL_ISR_MAX - UCOS_NUM_HAL_ISR_MIN + 1)
#define UCOS_NUM_HAL_VSR_EXCEPTION_COUNT 8
//--------------------------------------------------------------------------

#define UCOS_NUM_HAL_RTC_PERIOD                100