📄 hal_i2c.h
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//--------------------------------------------------------------------------// I2C bus registers#define UCOS_REG_I2CDR 0xE0000800 /* 8bit acess data*/#define UCOS_REG_I2CCR 0xE0000804 /* 8bit acess control*/#define UCOS_REG_I2CSR 0xE0000808 /* 8bit acess status*/#define UCOS_REG_I2CGR 0xE000080c /* 16bit acess clock*/#define I2CCR_ENABLE 0x01#define I2CCR_ACK 0x02#define I2CCR_STOP 0x04#define I2CCR_START 0x08#define I2CCR_IEN 0x10#define I2CSR_ACKF 0x01#define I2CSR_DRF 0x02#define I2CSR_TEND 0x04#define I2CSR_BUSY 0x08#define I2C_WRITE 0#define I2C_READ 1#define ERR_NODEV 1#define ERR_TIMEOUT 2#define SPD_DEV 0x50 //0b01010000#define SPD_DEV2 0x51 //0b01010001#define HCI_DEV 0x57 //0b01010111#define RTC_DEV 0x68 //0b01101000/* SPD */#define SPD_DRAM_ROW 3#define SPD_DRAM_COL 4#define SPD_DRAM_CHIP 5#define SPD_DRAM_REFRESH_RATE 12 /* Define it by us */#define SPD_DRAM_MB_LEN 16#define SPD_DRAM_BANK 17#define SPD_DRAM_CAS_LATENCY 18 /* CAS_LATENCY */#define SPD_DRAM_TRWL 20 /* Write precharge time * Write Latency */#define SPD_DRAM_TPC 27 /* RAS precharge time * Min Row Precharge Time TRP */#define SPD_DRAM_RRD 28 /* Min Row active to Row active TRRD*/#define SPD_DRAM_RCD 29 /* RCD RAS-CAS delay */#define SPD_DRAM_TRAS 30 /* TRAS RAS asserte time */#define SPD_DRAM_DENSITY 31 /* Density of each row *//* HCI */#define HCI_CHIP_2BUS_WIDTH 11 /* bit7--4:0:8byte 1:16byte 2:32byte */#define HCI_CHIP_2FLASH_ADDR 14 /* bit7--0:A31--A24 */#define HCI_CHIP_3BUS_WIDTH 147 /* bit7--4:0:8byte 1:16byte 2:32byte */#define HCI_CHIP_3FLASH_ADDR 150 /* bit7--0:A31--A24 */#define HCI_CHIP_TYPE 16 /* 0:DIMM 1:SODIMM 2:chip */#define HCI_CHIP_CHIP 29 /* Chip Location:CS */#define HCI_CHIP_ROW 17#define HCI_CHIP_COL 18#define HCI_CHIP_BANK 19#define HCI_CHIP_TRAS 20 /* RAS pulse width:TRAS */#define HCI_CHIP_RCD 21 /* min RAS-CAS delay:RCD */#define HCI_CHIP_TPC 22 /* Min RAS Precharge Time:TPC */#define HCI_CHIP_TRWL 23 /* Write Latency:TRWL */#define HCI_CHIP_RRD 24 /* Min RAS cycle time:TRRD*/#define HCI_CHIP_CAS_LATENCY 25 /* CAS latency:TCL */#define HCI_CHIP_REFRESH_RATE 27 #define HCI_CHIP_MB_LEN 28 /* burst length */#define HCI_CHIP_SIZE 30 /* memory size */#define HCI_CHIP_VERSION 120 /* version */#define HCI_CHIP_MAC 64 /* mac address,used 6 byte */#define HCI_VERSION_NULL 0xffffffff#if !defined(__ASSEMBLE__)#define I2CGR_VALUE 63 /* 80M / (16 * 80K(BautRate)) - 1 */#define REG16(addr) (*((unsigned short volatile *)(addr)))#define REG8(addr) (*((unsigned char volatile *)(addr)))#define i2c_start() \do { \ REG8(UCOS_REG_I2CCR) |= I2CCR_START; \} while (0)#define i2c_stop() \do { \ REG8(UCOS_REG_I2CCR) |= I2CCR_STOP; \} while (0)#define i2c_stop2() \do { \ REG8(UCOS_REG_I2CCR) &= ~I2CCR_ENABLE; \ REG8(UCOS_REG_I2CCR) |= I2CCR_ENABLE; \} while (0)#define i2c_enable() \do { \ REG8(UCOS_REG_I2CCR) |= I2CCR_ENABLE; \} while (0)#define i2c_disable() \do { \ REG8(UCOS_REG_I2CCR) &= ~I2CCR_ENABLE; \} while (0)#define i2c_set_ack() \do { \ REG8(UCOS_REG_I2CCR) &= ~I2CCR_ACK; \} while (0)#define i2c_set_nack() \do { \ REG8(UCOS_REG_I2CCR) |= I2CCR_ACK; \} while (0)#define i2c_set_drf() \do { \ REG8(UCOS_REG_I2CSR) |= I2CSR_DRF; \} while (0)#define i2c_clear_drf() \do { \ REG8(UCOS_REG_I2CSR) &= ~I2CSR_DRF; \} while (0)#define i2c_check_ack() (!(REG8(UCOS_REG_I2CSR) & I2CSR_ACKF))#define i2c_check_transmit_end() (REG8(UCOS_REG_I2CSR) & I2CSR_TEND)#define i2c_check_drf() (REG8(UCOS_REG_I2CSR) & I2CSR_DRF)#define i2c_read() REG8(UCOS_REG_I2CDR)#define i2c_write(val) \do { \ REG8(UCOS_REG_I2CDR) = (val); \} while (0);#define i2c_set_clock() \do { \ REG16(UCOS_REG_I2CGR) = I2CGR_VALUE; \} while (0);#endif
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