hal_superio.h

ucos 在arca方舟芯片（mips）上的移植。

#define UCOS_NUM_HAL_SER0_BASE 0xa80003f8
#define UCOS_NUM_HAL_SER1_BASE 0xa80002f8
#define UCOS_NUM_HAL_INTERRUPT_SER0 0x1b
#define UCOS_NUM_HAL_INTERRUPT_SER1 0x1c

#define UCOS_NUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD 115200
// LCR
#define UART_16550_LCR_DLAB	0x80	/* Divisor latch access bit */
#define UART_16550_LCR_SBC	0x40	/* Set break control */
#define UART_16550_LCR_SPAR	0x20	/* Stick parity (?) */
#define UART_16550_LCR_EPAR	0x10	/* Even parity select */
#define UART_16550_LCR_PARITY	0x08	/* Parity Enable */
#define UART_16550_LCR_STOP	0x04	/* Stop bits:
					   0=1 stop bit, 1= 2 stop bits */
#define UART_16550_LCR_WLEN5	0x00	/* Wordlength: 5 bits */
#define UART_16550_LCR_WLEN6	0x01	/* Wordlength: 6 bits */
#define UART_16550_LCR_WLEN7	0x02	/* Wordlength: 7 bits */
#define UART_16550_LCR_WLEN8	0x03	/* Wordlength: 8 bits */

// LSR
#define UART_16550_LSR_RFER	0x80	/* Transmitter empty */
#define UART_16550_LSR_TEMT	0x40	/* Transmitter empty */
#define UART_16550_LSR_THRE	0x20	/* Transmit-hold-register empty */
#define UART_16550_LSR_BI	0x10	/* Break interrupt indicator */
#define UART_16550_LSR_FE	0x08	/* Frame error indicator */
#define UART_16550_LSR_PE	0x04	/* Parity error indicator */
#define UART_16550_LSR_OE	0x02	/* Overrun error indicator */
#define UART_16550_LSR_DR	0x01	/* Receiver data ready */

// FCR
#define UART_16550_FCR_DMS	0x08
#define UART_16550_FCR_TFLS	0x04
#define UART_16550_FCR_RFLS	0x02
#define UART_16550_FCR_FE	0x01
#define UART_16550_ENB		UART_FCR_UUE

#define UART_16550_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
#define UART_16550_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
#define UART_16550_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
#define UART_16550_FCR_DMA_SELECT	0x08 /* For DMA applications */
#define UART_16550_FCR_UUE		0x10

#define UART_16550_FCR_TRIGGER_MASK	0xC0 /* Mask for FIFO trigger range */
#define UART_16550_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
#define UART_16550_FCR_TRIGGER_16	0x40 /* Mask for trigger set at 4 */
#define UART_16550_FCR_TRIGGER_32	0x80 /* Mask for trigger set at 8 */
#define UART_16550_FCR_TRIGGER_60	0xC0 /* Mask for trigger set at 14 */

#define UART_16550_FCR6_R_TRIGGER_8	0x00 /* receive trigger set at 1 */
#define UART_16550_FCR6_R_TRIGGER_16	0x40 /* receive trigger set at 4 */
#define UART_16550_FCR6_R_TRIGGER_24	0x80 /* receive trigger set at 8 */
#define UART_16550_FCR6_R_TRIGGER_28	0xC0 /* receive trigger set at 14 */
#define UART_16550_FCR6_T_TRIGGER_16	0x00 /* transmit trigger set at 16 */
#define UART_16550_FCR6_T_TRIGGER_8	0x10 /* transmit trigger set at 8 */
#define UART_16550_FCR6_T_TRIGGER_24	0x20 /* transmit trigger set at 24 */
#define UART_16550_FCR6_T_TRIGGER_30	0x30 /* transmit trigger set at 30 */
// TI 16750 definitions
#define UART_16550_FCR7_64BYTE		0x20 /* Go into 64 byte mode */

#if !defined(__ASSEMBLY__)

typedef struct {
    unsigned char* base;
    unsigned int msec_timeout;
    int isr_vector;
    int baud;
} channel_data_t;

static channel_data_t diag_channels[2] = {
    {
	(unsigned char*)(UCOS_NUM_HAL_SER0_BASE),
	1000, UCOS_NUM_HAL_INTERRUPT_SER0,
	UCOS_NUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
    },
    {
	(unsigned char*)(UCOS_NUM_HAL_SER1_BASE),
	1000, UCOS_NUM_HAL_INTERRUPT_SER1,
	UCOS_NUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
    },
};

void ucos_hal_superio_serial_init(void);
void ucos_hal_superio_serial_putc(void *__ch_data, char c);
#endif