📄 s5h_common_reg.h
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*********************************************/
#define SAIU_BASE S5H5002_SDRAM_BASE + 0x3CA00000
#define rSAIUCLKCON (*(volatile UINT *) (SAIU_BASE + 0x00))
#define rSAIUTXCON (*(volatile UINT *) (SAIU_BASE + 0x04))
#define rSAIUTXCOM (*(volatile UINT *) (SAIU_BASE + 0x08))
#define rSAIUTXDB0 (*(volatile UINT *) (SAIU_BASE + 0x10))
#define rSAIUTXDB1 (*(volatile UINT *) (SAIU_BASE + 0x14))
#define rSAIUTXDB2 (*(volatile UINT *) (SAIU_BASE + 0x18))
#define rSAIUTXDB3 (*(volatile UINT *) (SAIU_BASE + 0x1C))
#define rSAIUTXDB4 (*(volatile UINT *) (SAIU_BASE + 0x20))
#define rSAIURXCON (*(volatile UINT *) (SAIU_BASE + 0x30))
#define rSAIURXCOM (*(volatile UINT *) (SAIU_BASE + 0x34))
#define rSAIURXDB (*(volatile UINT *) (SAIU_BASE + 0x38))
/*********************************************
* SPDIF Register
*********************************************/
#define SPDIF_BASE S5H5002_SDRAM_BASE + 0x3CB00000
#define rSPDCLKCON (*(volatile UINT *) (SPDIF_BASE + 0x00))
#define rSPDCON (*(volatile UINT *) (SPDIF_BASE + 0x04))
#define rSPDBSTAS (*(volatile UINT *) (SPDIF_BASE + 0x08))
#define rSPDCSTAS (*(volatile UINT *) (SPDIF_BASE + 0x0C))
#define rSPDDAT (*(volatile UINT *) (SPDIF_BASE + 0x10))
#define rSPDCNT (*(volatile UINT *) (SPDIF_BASE + 0x14))
/*********************************************
* SPI Register
*********************************************/
#define SPI_BASE 0x39A000
#define rSPCLKCON (*(volatile UINT *) (SPI_BASE + 0x00))
#define rSPCON (*(volatile UINT *) (SPI_BASE + 0x04))
#define rSPSTA (*(volatile UINT *) (SPI_BASE + 0x08))
#define rSPPIN (*(volatile UINT *) (SPI_BASE + 0x0C))
#define rSPTDAT (*(volatile UINT *) (SPI_BASE + 0x10))
#define rSPRDAT (*(volatile UINT *) (SPI_BASE + 0x14))
#define rSPPRE (*(volatile UINT *) (SPI_BASE + 0x18))
/*********************************************
* GPIO Register
*********************************************/
#if 0
#define GPIO_BASE S5H5002_SDRAM_BASE + 0x3CF00000
#define rPCON0 (*(volatile UINT *) (GPIO_BASE + 0x00))
#define rPDAT0 (*(volatile UINT *) (GPIO_BASE + 0x04))
#define rP0PUR (*(volatile UINT *) (GPIO_BASE + 0x08))
#define rPCON1 (*(volatile UINT *) (GPIO_BASE + 0x10))
#define rPDAT1 (*(volatile UINT *) (GPIO_BASE + 0x14))
#define rP1PUR (*(volatile UINT *) (GPIO_BASE + 0x18))
#define rPCON2 (*(volatile UINT *) (GPIO_BASE + 0x20))
#define rPDAT2 (*(volatile UINT *) (GPIO_BASE + 0x24))
#define rP2PUR (*(volatile UINT *) (GPIO_BASE + 0x28))
#define rPCON3 (*(volatile UINT *) (GPIO_BASE + 0x30))
#define rPDAT3 (*(volatile UINT *) (GPIO_BASE + 0x34))
#define rP3PUR (*(volatile UINT *) (GPIO_BASE + 0x38))
#define rPCON4 (*(volatile UINT *) (GPIO_BASE + 0x40))
#define rPDAT4 (*(volatile UINT *) (GPIO_BASE + 0x44))
#define rP4PUR (*(volatile UINT *) (GPIO_BASE + 0x48))
#define rPCON5 (*(volatile UINT *) (GPIO_BASE + 0x50))
#define rPDAT5 (*(volatile UINT *) (GPIO_BASE + 0x54))
#define rP5PUR (*(volatile UINT *) (GPIO_BASE + 0x58))
#define rPCON6 (*(volatile UINT *) (GPIO_BASE + 0x60))
#define rPDAT6 (*(volatile UINT *) (GPIO_BASE + 0x64))
#define rP6PUR (*(volatile UINT *) (GPIO_BASE + 0x68))
#define rPCON7 (*(volatile UINT *) (GPIO_BASE + 0x70))
#define rPDAT7 (*(volatile UINT *) (GPIO_BASE + 0x74))
#define rP7PUR (*(volatile UINT *) (GPIO_BASE + 0x78))
#define rPCON8 (*(volatile UINT *) (GPIO_BASE + 0x80))
#define rPDAT8 (*(volatile UINT *) (GPIO_BASE + 0x84))
#define rP8PUR (*(volatile UINT *) (GPIO_BASE + 0x88))
#else
#define GPIO_BASE 0x39e000
#define rPCON0_H (*(volatile unsigned int *) (GPIO_BASE+0x000))
#define rPCON0_L (*(volatile unsigned int *) (GPIO_BASE+0x002))
#define rPDAT0_H (*(volatile unsigned int *) (GPIO_BASE+0x004))
#define rPDAT0_L (*(volatile unsigned int *) (GPIO_BASE+0x006))
#if 1
#define rPCON1_H (*(volatile unsigned int *) (GPIO_BASE+0x008))
#define rPCON1_L (*(volatile unsigned int *) (GPIO_BASE+0x00a))
#define rPDAT1_H (*(volatile unsigned int *) (GPIO_BASE+0x00c))
#define rPDAT1_L (*(volatile unsigned int *) (GPIO_BASE+0x00e))
#else
#define rP0PUR_H (*(volatile unsigned int *) (GPIO_BASE+0x008))
#define rP0PUR_L (*(volatile unsigned int *) (GPIO_BASE+0x00a))
#define rPCON1_H (*(volatile unsigned int *) (GPIO_BASE+0x010))
#define rPCON1_L (*(volatile unsigned int *) (GPIO_BASE+0x012))
#define rPDAT1_H (*(volatile unsigned int *) (GPIO_BASE+0x014))
#define rPDAT1_L (*(volatile unsigned int *) (GPIO_BASE+0x016))
#define rP1PUR_H (*(volatile unsigned int *) (GPIO_BASE+0x018))
#define rP1PUR_L (*(volatile unsigned int *) (GPIO_BASE+0x01a))
#endif
#define rPCON2_H (*(volatile unsigned int *) (GPIO_BASE+0x010))
#define rPCON2_L (*(volatile unsigned int *) (GPIO_BASE+0x012))
#define rPDAT2_H (*(volatile unsigned int *) (GPIO_BASE+0x014))
#define rPDAT2_L (*(volatile unsigned int *) (GPIO_BASE+0x016))
//#define rP2PUR_H (*(volatile unsigned int *) (GPIO_BASE+0x018))
//#define rP2PUR_L (*(volatile unsigned int *) (GPIO_BASE+0x01a))
#define rPCON3_H (*(volatile unsigned int *) (GPIO_BASE+0x018))
#define rPCON3_L (*(volatile unsigned int *) (GPIO_BASE+0x01a))
#define rPDAT3_H (*(volatile unsigned int *) (GPIO_BASE+0x01c))
#define rPDAT3_L (*(volatile unsigned int *) (GPIO_BASE+0x01e))
#if 0
#define rP3PUR_H (*(volatile unsigned int *) (GPIO_BASE+0x038))
#define rP3PUR_L (*(volatile unsigned int *) (GPIO_BASE+0x03a))
#define rPCON4_H (*(volatile unsigned int *) (GPIO_BASE+0x040))
#define rPCON4_L (*(volatile unsigned int *) (GPIO_BASE+0x042))
#define rPDAT4_H (*(volatile unsigned int *) (GPIO_BASE+0x044))
#define rPDAT4_L (*(volatile unsigned int *) (GPIO_BASE+0x046))
#define rP4PUR_H (*(volatile unsigned int *) (GPIO_BASE+0x048))
#define rP4PUR_L (*(volatile unsigned int *) (GPIO_BASE+0x04a))
#define rPCON5_H (*(volatile unsigned int *) (GPIO_BASE+0x050))
#define rPCON5_L (*(volatile unsigned int *) (GPIO_BASE+0x052))
#define rPDAT5_H (*(volatile unsigned int *) (GPIO_BASE+0x054))
#define rPDAT5_L (*(volatile unsigned int *) (GPIO_BASE+0x056))
#define rP5PUR_H (*(volatile unsigned int *) (GPIO_BASE+0x058))
#define rP5PUR_L (*(volatile unsigned int *) (GPIO_BASE+0x05a))
#define rPCON6_H (*(volatile unsigned int *) (GPIO_BASE+0x060))
#define rPCON6_L (*(volatile unsigned int *) (GPIO_BASE+0x062))
#define rPDAT6_H (*(volatile unsigned int *) (GPIO_BASE+0x064))
#define rPDAT6_L (*(volatile unsigned int *) (GPIO_BASE+0x066))
#define rP6PUR_H (*(volatile unsigned int *) (GPIO_BASE+0x068))
#define rP6PUR_L (*(volatile unsigned int *) (GPIO_BASE+0x06a))
#define rPCON7_H (*(volatile unsigned int *) (GPIO_BASE+0x070))
#define rPCON7_L (*(volatile unsigned int *) (GPIO_BASE+0x072))
#define rPDAT7_H (*(volatile unsigned int *) (GPIO_BASE+0x074))
#define rPDAT7_L (*(volatile unsigned int *) (GPIO_BASE+0x076))
#define rP7PUR_H (*(volatile unsigned int *) (GPIO_BASE+0x078))
#define rP7PUR_L (*(volatile unsigned int *) (GPIO_BASE+0x07a))
#define rPCON8_H (*(volatile unsigned int *) (GPIO_BASE+0x080))
#define rPCON8_L (*(volatile unsigned int *) (GPIO_BASE+0x082))
#define rPDAT8_H (*(volatile unsigned int *) (GPIO_BASE+0x084))
#define rPDAT8_L (*(volatile unsigned int *) (GPIO_BASE+0x086))
#define rP8PUR_H (*(volatile unsigned int *) (GPIO_BASE+0x088))
#define rP8PUR_L (*(volatile unsigned int *) (GPIO_BASE+0x08a))
#define rPCON9_H (*(volatile unsigned int *) (GPIO_BASE+0x090))
#define rPCON9_L (*(volatile unsigned int *) (GPIO_BASE+0x092))
#define rPDAT9_H (*(volatile unsigned int *) (GPIO_BASE+0x094))
#define rPDAT9_L (*(volatile unsigned int *) (GPIO_BASE+0x096))
#define rP9PUR_H (*(volatile unsigned int *) (GPIO_BASE+0x098))
#define rP9PUR_L (*(volatile unsigned int *) (GPIO_BASE+0x09a))
#define rPCON10_H (*(volatile unsigned int *) (GPIO_BASE+0x0A0))
#define rPCON10_L (*(volatile unsigned int *) (GPIO_BASE+0x0A2))
#define rPDAT10_H (*(volatile unsigned int *) (GPIO_BASE+0x0A4))
#define rPDAT10_L (*(volatile unsigned int *) (GPIO_BASE+0x0A6))
#define rP10PUR_H (*(volatile unsigned int *) (GPIO_BASE+0x0A8))
#define rP10PUR_L (*(volatile unsigned int *) (GPIO_BASE+0x0Aa))
#define rEXTPOL_H (*(volatile unsigned int *) (GPIO_BASE+0x018))
#define rEXTPOL_L (*(volatile unsigned int *) (GPIO_BASE+0x01a))
#endif
#endif
/*********************************************
* IR Register
*********************************************/
#if 0
#define IR_BASE S5H5002_SDRAM_BASE + 0x3C400000
#define rIRCON (*(volatile UINT *) (IR_BASE + 0x00))
#define rIRDAT (*(volatile UINT *) (IR_BASE + 0x04))
#define rIRCNT (*(volatile UINT *) (IR_BASE + 0x08))
#else
#define IR_BASE 0x388000
#define rIRCON_H (*(volatile unsigned int *) (IR_BASE + 0x00))
#define rIRCON_L (*(volatile unsigned int *) (IR_BASE + 0x02))
#define rIRDAT_H (*(volatile unsigned int *) (IR_BASE + 0x04))
#define rIRDAT_L (*(volatile unsigned int *) (IR_BASE + 0x06))
#define rIRCNT_H (*(volatile unsigned int *) (IR_BASE + 0x08))
#define rIRCNT_L (*(volatile unsigned int *) (IR_BASE + 0x0A))
#endif
/*********************************************
* IIS Register
*********************************************/
#define PWMUnit_BASE 0x394000
#define rPWM_CONTROL1_H (*(volatile unsigned int *) (PWMUnit_BASE+0x004))
#define rPWM_CONTROL1_L (*(volatile unsigned int *) (PWMUnit_BASE+0x006))
#define rPWM_CONTROL2_H (*(volatile unsigned int *) (PWMUnit_BASE+0x008))
#define rPWM_CONTROL2_L (*(volatile unsigned int *) (PWMUnit_BASE+0x00A))
/*********************************************
* CSDMA Register
*********************************************/
#define CSDMA_BASE 0x318000
#define rCSDMA_SAR_H (*(volatile unsigned int *) (CSDMA_BASE+0x0))
#define rCSDMA_SAR_L (*(volatile unsigned int *) (CSDMA_BASE+0x002))
#define rCSDMA_DAR1_H (*(volatile unsigned int *) (CSDMA_BASE+0x004))
#define rCSDMA_DAR1_L (*(volatile unsigned int *) (CSDMA_BASE+0x006))
#define rCSDMA_DAR2_H (*(volatile unsigned int *) (CSDMA_BASE+0x008))
#define rCSDMA_DAR2_L (*(volatile unsigned int *) (CSDMA_BASE+0x00A))
#define rCSDMA_WC_H (*(volatile unsigned int *) (CSDMA_BASE+0x00c))
#define rCSDMA_WC_L (*(volatile unsigned int *) (CSDMA_BASE+0x00e))
#define rCSDMA_CONF_H (*(volatile unsigned int *) (CSDMA_BASE+0x010))
#define rCSDMA_CONF_L (*(volatile unsigned int *) (CSDMA_BASE+0x012))
#define rCSDMA_CMD_H (*(volatile unsigned int *) (CSDMA_BASE+0x014))
#define rCSDMA_CMD_L (*(volatile unsigned int *) (CSDMA_BASE+0x016))
#define rCSDMA_CRWC_H (*(volatile unsigned int *) (CSDMA_BASE+0x018))
#define rCSDMA_CRWC_L (*(volatile unsigned int *) (CSDMA_BASE+0x01a))
/*********************************************
* ADM Register
*********************************************/
#define SFR_BASE 0x2C0000
#define rXBASE_H (*(volatile unsigned int *) (SFR_BASE+0x36))
#define rXBASE_L (*(volatile unsigned int *) (SFR_BASE+0x38))
#define rS0BASE_H (*(volatile unsigned int *) (SFR_BASE+0x3E))
#define rS0BASE_L (*(volatile unsigned int *) (SFR_BASE+0x40))
#define rS1BASE_H (*(volatile unsigned int *) (SFR_BASE+0x42))
#define rS1BASE_L (*(volatile unsigned int *) (SFR_BASE+0x44))
/*********************************************
* Interrupt vector
*********************************************/
#define EINT0 0 // External Interrupt 0
#define EINT1 1 // External Interrupt 1
#define EINT2 2 // External Interrupt 2
#define IR_INT 3 // Remote control signal
#define EINTG 4 // External Interrupt Group(3-7)
#define INT_TIMERA 5 // Timer A Interrupt
#define WATCHDOG 6 // Watchdog Timer Interrupt
#define INT_TIMERB 7 // Timer B Interrupt
#define INT_TIMERC 8 // Timer C Interrupt
#define INT_TIMERD 9 // Timer D Interrupt
#define INT_ADC 31 // ADC EOC(End Of Conversion) Interrupt
//=================================================================
// Macro Fucntions
//=================================================================
//extern void Intmod_Irq(unsigned long x);
//extern void Intmod_Fiq(unsigned long x);
//extern void Disable_Int(unsigned long x);
//extern void Enable_Int(unsigned long x);
//extern void Intclr_Scr(unsigned long x);
//extern void Intclr_Pnd(unsigned long x);
extern void Intmod_Fiq(unsigned long x);
extern void Intmod_Irq(unsigned long x);
extern void Disable_Int(unsigned long x);
extern void Enable_Int(unsigned long x);
extern void Intclr_Scr(unsigned long x);
extern void Intclr_Pnd(unsigned long x);
//=================================================================
// Default Values
//=================================================================
#define MAXHNDLRS 32 // Interrupt source (32)
#define ALL_MASK 0x0 // New version (1: Enable)
#define ALL_IRQ 0x0
#define ALL_FIQ 0xffffffff
#define ALL_CLR 0xffffffff
#ifdef __cplusplus
}
#endif
#endif /* _S5H_COMMON_REG_H_ */
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