s5h_common_reg.h

三星ic 9980的源代码. 718版.

/******************************************************************************
 *   Filename    : S5h_common_reg.h
 *   Start date  : 
 *   By          : Chongkun Lee
 *   Contact     : [e-mail]
 *   Description : S5H5002 Common registers
 *
 ******************************************************************************
 */
#ifndef	_S5H_COMMON_REG_H_
#define	_S5H_COMMON_REG_H_


/********************************************* 
 *   INCLUDE
 *********************************************/

#ifdef __cplusplus
extern "C" {
#endif

#ifndef S5H5002_SDRAM_BASE
#define S5H5002_SDRAM_BASE	0
#endif


/******************************************************************************
 *   AHB	
 ******************************************************************************/

/********************************************* 
 *   MIU Register	
 *********************************************/
#define		MIU_BASE		0x304000
#define		rMIUS01PARA_H	(*(volatile unsigned int *) (MIU_BASE+0x014))
#define		rMIUS01PARA_L	(*(volatile unsigned int *) (MIU_BASE+0x016))
#define		rMIUS23PARA_H	(*(volatile unsigned int *) (MIU_BASE+0x018))
#define		rMIUS23PARA_L	(*(volatile unsigned int *) (MIU_BASE+0x01a))
#define		rMIUSSIZE_H		(*(volatile unsigned int *) (MIU_BASE+0x01C))
#define		rMIUSSIZE_L		(*(volatile unsigned int *) (MIU_BASE+0x01E))



/********************************************* 
 *   I/O Dma Register	
 *********************************************/
#define DMA_BASE		 S5H5002_SDRAM_BASE + 0x38400000
 
#define rDMABASE0		(*(volatile UINT *) (DMA_BASE + 0x00))
#define rDMACON0		(*(volatile UINT *) (DMA_BASE + 0x04))
#define rDMATCNT0		(*(volatile UINT *) (DMA_BASE + 0x08))
#define rDMACADDR0		(*(volatile UINT *) (DMA_BASE + 0x0C))
#define rDMACTCNT0		(*(volatile UINT *) (DMA_BASE + 0x10))
#define rDMACOM0		(*(volatile UINT *) (DMA_BASE + 0x14))
#define rDMANOFF0		(*(volatile UINT *) (DMA_BASE + 0x18))

#define rDMABASE1		(*(volatile UINT *) (DMA_BASE + 0x20))
#define rDMACON1		(*(volatile UINT *) (DMA_BASE + 0x24))
#define rDMATCNT1		(*(volatile UINT *) (DMA_BASE + 0x28))
#define rDMACADDR1		(*(volatile UINT *) (DMA_BASE + 0x2C))
#define rDMACTCNT1		(*(volatile UINT *) (DMA_BASE + 0x30))
#define rDMACOM1		(*(volatile UINT *) (DMA_BASE + 0x34))

#define rDMABASE2		(*(volatile UINT *) (DMA_BASE + 0x40))
#define rDMACON2		(*(volatile UINT *) (DMA_BASE + 0x44))
#define rDMATCNT2		(*(volatile UINT *) (DMA_BASE + 0x48))
#define rDMACADDR2		(*(volatile UINT *) (DMA_BASE + 0x4C))
#define rDMACTCNT2		(*(volatile UINT *) (DMA_BASE + 0x50))
#define rDMACOM2		(*(volatile UINT *) (DMA_BASE + 0x54))

#define rDMABASE3		(*(volatile UINT *) (DMA_BASE + 0x60))
#define rDMACON3		(*(volatile UINT *) (DMA_BASE + 0x64))
#define rDMATCNT3		(*(volatile UINT *) (DMA_BASE + 0x68))
#define rDMACADDR3		(*(volatile UINT *) (DMA_BASE + 0x6C))
#define rDMACTCNT3		(*(volatile UINT *) (DMA_BASE + 0x70))
#define rDMACOM3		(*(volatile UINT *) (DMA_BASE + 0x74))

#define rDMAALLST		(*(volatile UINT *) (DMA_BASE + 0x100))


/********************************************* 
 *   INTERRUPT Register	
 *********************************************/

#define		intcUnit_BASE	0x338000                             
#define		rSRCPND_H		(*(volatile unsigned int *) (intcUnit_BASE+0x000))
#define		rSRCPND_L		(*(volatile unsigned int *) (intcUnit_BASE+0x002))
#define		rINTMOD_H		(*(volatile unsigned int *) (intcUnit_BASE+0x004))
#define		rINTMOD_L		(*(volatile unsigned int *) (intcUnit_BASE+0x006))
#define		rINTMASK_H		(*(volatile unsigned int *) (intcUnit_BASE+0x008))
#define		rINTMASK_L		(*(volatile unsigned int *) (intcUnit_BASE+0x00a))
#define		rPRIORITY_H		(*(volatile unsigned int *) (intcUnit_BASE+0x00C))
#define		rPRIORITY_L		(*(volatile unsigned int *) (intcUnit_BASE+0x00e))
#define		rINTPND_H		(*(volatile unsigned int *) (intcUnit_BASE+0x010))
#define		rINTPND_L		(*(volatile unsigned int *) (intcUnit_BASE+0x012))
#define		rINTOFFSET_H	(*(volatile unsigned int *) (intcUnit_BASE+0x014))
#define		rINTOFFSET_L	(*(volatile unsigned int *) (intcUnit_BASE+0x016))
#define		rEINTPOL_H		(*(volatile unsigned int *) (intcUnit_BASE+0x018))
#define		rEINTPOL_L		(*(volatile unsigned int *) (intcUnit_BASE+0x01a))
#define		rEINTPND_H		(*(volatile unsigned int *) (intcUnit_BASE+0x01C))
#define		rEINTPND_L		(*(volatile unsigned int *) (intcUnit_BASE+0x01e))
#define		rEINTMASK_H		(*(volatile unsigned int *) (intcUnit_BASE+0x020))
#define		rEINTMASK_L		(*(volatile unsigned int *) (intcUnit_BASE+0x022))

//#define EINT0_DSPIRQ	0x01 	/*EINT0*/
//#define BIT_EINT0	0x01

/********************************************* 
 *   NAND FLASH Register	
 *********************************************/
#define NF_BASE			 S5H5002_SDRAM_BASE + 0x39F00000

#define rNFCONF			(*(volatile UINT *) (NF_BASE + 0x00))
#define rNFCMD			(*(volatile UINT *) (NF_BASE + 0x04))
#define rNFADDR			(*(volatile UINT *) (NF_BASE + 0x08))
#define rNFDATA			(*(volatile UINT *) (NF_BASE + 0x0C))
#define rNFSTAT			(*(volatile UINT *) (NF_BASE + 0x10))
#define rNFECC			(*(volatile UINT *) (NF_BASE + 0x14))



/******************************************************************************
 *   APB	
 ******************************************************************************/

/********************************************* 
 *   FE Micom Register	
 *********************************************/
#define MIF_BASE		S5H5002_SDRAM_BASE + 0x3C300000
 
#define rMIFCOM			(*(volatile UINT *) (MIF_BASE + 0x00)) 
#define rMIFST			(*(volatile UINT *) (MIF_BASE + 0x04))
#define SERVO_ADDR		(*(volatile UINT *) (MIF_BASE + 0x00))
#define SERVO_DATA		(*(volatile UINT *) (MIF_BASE + 0x00))
#define DSSP_ADDR		(*(volatile UINT *) (MIF_BASE + 0x00))
#define DSSP_DATA		(*(volatile UINT *) (MIF_BASE + 0x00))
#define rMIFPARA		(*(volatile UINT *) (MIF_BASE + 0x08))
#define rPEXTCOM		(*(volatile UINT *) (MIF_BASE + 0x10))
#define rPEXTST			(*(volatile UINT *) (MIF_BASE + 0x14))
#define rPEXTPARA		(*(volatile UINT *) (MIF_BASE + 0x18))


/********************************************* 
 *   Clock Register	
 *********************************************/

#define		clkUnit_BASE	0x38a000                                  
#define		rCLKCON1_H		(*(volatile unsigned int *) (clkUnit_BASE+0x000))
#define		rCLKCON1_L		(*(volatile unsigned int *) (clkUnit_BASE+0x002))
#define		rCLKCON2_H		(*(volatile unsigned int *) (clkUnit_BASE+0x004))
#define		rCLKCON2_L		(*(volatile unsigned int *) (clkUnit_BASE+0x006))
#define		rPLL0PMS_H		(*(volatile unsigned int *) (clkUnit_BASE+0x008))
#define		rPLL0PMS_L		(*(volatile unsigned int *) (clkUnit_BASE+0x00a))
#define		rPLL1PMS_H		(*(volatile unsigned int *) (clkUnit_BASE+0x00c))
#define		rPLL1PMS_L		(*(volatile unsigned int *) (clkUnit_BASE+0x00e))
#define		rPLL2PMS_H		(*(volatile unsigned int *) (clkUnit_BASE+0x010))
#define		rPLL2PMS_L		(*(volatile unsigned int *) (clkUnit_BASE+0x012))
#define		rPLL0LCNT_H		(*(volatile unsigned int *) (clkUnit_BASE+0x018))
#define		rPLL0LCNT_L		(*(volatile unsigned int *) (clkUnit_BASE+0x01a))
#define		rPLL1LCNT_H		(*(volatile unsigned int *) (clkUnit_BASE+0x01c))
#define		rPLL1LCNT_L		(*(volatile unsigned int *) (clkUnit_BASE+0x01e))
#define		rPLL2LCNT_H		(*(volatile unsigned int *) (clkUnit_BASE+0x020))
#define		rPLL2LCNT_L		(*(volatile unsigned int *) (clkUnit_BASE+0x022))
#define		rPLLLOCK_H		(*(volatile unsigned int *) (clkUnit_BASE+0x028))
#define		rPLLLOCK_L		(*(volatile unsigned int *) (clkUnit_BASE+0x02a))
#define		rPLLCON_H		(*(volatile unsigned int *) (clkUnit_BASE+0x02c))
#define		rPLLCON_L		(*(volatile unsigned int *) (clkUnit_BASE+0x02e))
#define		rPWRCON_H		(*(volatile unsigned int *) (clkUnit_BASE+0x030))
#define		rPWRCON_L		(*(volatile unsigned int *) (clkUnit_BASE+0x032))
#define		rSWRCON_H		(*(volatile unsigned int *) (clkUnit_BASE+0x034))
#define		rSWRCON_L		(*(volatile unsigned int *) (clkUnit_BASE+0x036))
#define		rRSTSR_H		(*(volatile unsigned int *) (clkUnit_BASE+0x038))
#define		rRSTSR_L		(*(volatile unsigned int *) (clkUnit_BASE+0x03a))
#define		rCKOCON_H		(*(volatile unsigned int *) (clkUnit_BASE+0x040))
#define		rCKOCON_L		(*(volatile unsigned int *) (clkUnit_BASE+0x042))
#define		rFEURST_H		(*(volatile unsigned int *) (clkUnit_BASE+0x050))
#define		rFEURST_L		(*(volatile unsigned int *) (clkUnit_BASE+0x052))


/********************************************* 
 *   TIMER Register	
 *********************************************/

#define		TIMER_BASE		0x38E000      

#define		rTACON_H		(*(volatile unsigned int *) (TIMER_BASE+0x000))
#define		rTACON_L		(*(volatile unsigned int *) (TIMER_BASE+0x002))
#define		rTACMD_H		(*(volatile unsigned int *) (TIMER_BASE+0x004))
#define		rTACMD_L		(*(volatile unsigned int *) (TIMER_BASE+0x006))
#define		rTADATA1_H		(*(volatile unsigned int *) (TIMER_BASE+0x008))
#define		rTADATA1_L		(*(volatile unsigned int *) (TIMER_BASE+0x00a))
#define		rTADATA2_H		(*(volatile unsigned int *) (TIMER_BASE+0x00C))
#define		rTADATA2_L		(*(volatile unsigned int *) (TIMER_BASE+0x00e))
#define		rTAPRE_H		(*(volatile unsigned int *) (TIMER_BASE+0x010))
#define		rTAPRE_L		(*(volatile unsigned int *) (TIMER_BASE+0x012))
#define		rTACNT_H		(*(volatile unsigned int *) (TIMER_BASE+0x014))
#define		rTACNT_L		(*(volatile unsigned int *) (TIMER_BASE+0x016))

#define		rTBCON_H		(*(volatile unsigned int *) (TIMER_BASE+0x020))
#define		rTBCON_L		(*(volatile unsigned int *) (TIMER_BASE+0x022))
#define		rTBCMD_H		(*(volatile unsigned int *) (TIMER_BASE+0x024))
#define		rTBCMD_L		(*(volatile unsigned int *) (TIMER_BASE+0x026))
#define		rTBDATA1_H		(*(volatile unsigned int *) (TIMER_BASE+0x028))
#define		rTBDATA1_L		(*(volatile unsigned int *) (TIMER_BASE+0x02a))
#define		rTBDATA2_H		(*(volatile unsigned int *) (TIMER_BASE+0x02C))
#define		rTBDATA2_L		(*(volatile unsigned int *) (TIMER_BASE+0x02e))
#define		rTBPRE_H		(*(volatile unsigned int *) (TIMER_BASE+0x030))
#define		rTBPRE_L		(*(volatile unsigned int *) (TIMER_BASE+0x032))
#define		rTBCNT_H		(*(volatile unsigned int *) (TIMER_BASE+0x034))
#define		rTBCNT_L		(*(volatile unsigned int *) (TIMER_BASE+0x036))

#define		rTCCON_H		(*(volatile unsigned int *) (TIMER_BASE+0x040))
#define		rTCCON_L		(*(volatile unsigned int *) (TIMER_BASE+0x042))
#define		rTCCMD_H		(*(volatile unsigned int *) (TIMER_BASE+0x044))
#define		rTCCMD_L		(*(volatile unsigned int *) (TIMER_BASE+0x046))
#define		rTCDATA1_H		(*(volatile unsigned int *) (TIMER_BASE+0x048))
#define		rTCDATA1_L		(*(volatile unsigned int *) (TIMER_BASE+0x04a))

#define		rTCPRE_H		(*(volatile unsigned int *) (TIMER_BASE+0x050))
#define		rTCPRE_L		(*(volatile unsigned int *) (TIMER_BASE+0x052))
#define		rTCCNT_H		(*(volatile unsigned int *) (TIMER_BASE+0x054))
#define		rTCCNT_L		(*(volatile unsigned int *) (TIMER_BASE+0x056))

#define		rTDCON_H		(*(volatile unsigned int *) (TIMER_BASE+0x060))
#define		rTDCON_L		(*(volatile unsigned int *) (TIMER_BASE+0x062))
#define		rTDCMD_H		(*(volatile unsigned int *) (TIMER_BASE+0x064))
#define		rTDCMD_L		(*(volatile unsigned int *) (TIMER_BASE+0x066))
#define		rTDDATA1_H		(*(volatile unsigned int *) (TIMER_BASE+0x068))
#define		rTDDATA1_L		(*(volatile unsigned int *) (TIMER_BASE+0x06a))
#define		rTDPRE_H		(*(volatile unsigned int *) (TIMER_BASE+0x070))
#define		rTDPRE_L		(*(volatile unsigned int *) (TIMER_BASE+0x072))
#define		rTDCNT_H		(*(volatile unsigned int *) (TIMER_BASE+0x074))
#define		rTDCNT_L		(*(volatile unsigned int *) (TIMER_BASE+0x076))


/***********************************************
 *	ADC register
 ***********************************************/
#define  scr_base	0x39c000
#define	rSCRCON_H		(*(volatile UINT *) (scr_base+ 0x0))
#define	rSCRCON_L		(*(volatile UINT *) (scr_base+ 0x2))
#define	rSCRCNT_H		(*(volatile UINT *) (scr_base+ 0x4))
#define	rSCRCNT_L		(*(volatile UINT *) (scr_base+ 0x6))
/********************************************* 
 *   WDT Register	
 *********************************************/
#define WDT_BASE		0x390000

#define rWDTCON_H			(*(volatile UINT *) (WDT_BASE + 0x00))
#define rWDTCON_L			(*(volatile UINT *) (WDT_BASE + 0x02))

#define rWDTCNT_H			(*(volatile UINT *) (WDT_BASE + 0x04))
#define rWDTCNT_L			(*(volatile UINT *) (WDT_BASE + 0x06))


/********************************************* 
 *   IIC Register	
 *********************************************/
#define I2S_BASE		0x392000//S5H5002_SDRAM_BASE + 0x3C900000
#define rI2CCON			(*(volatile UINT *) (I2S_BASE + 0x00))
#define rI2CSTAT		(*(volatile UINT *) (I2S_BASE + 0x04))
#define rI2CADD			(*(volatile UINT *) (I2S_BASE + 0x08))
#define rI2CDS			(*(volatile UINT *) (I2S_BASE + 0x0C))                                                       

#define rI2CCON_H			(*(volatile UINT *) (I2S_BASE + 0x00))
#define rI2CCON_L			(*(volatile UINT *) (I2S_BASE + 0x02))
#define rI2CSTAT_H		(*(volatile UINT *) (I2S_BASE + 0x04))
#define rI2CSTAT_L		(*(volatile UINT *) (I2S_BASE + 0x06))
#define rI2CADD_H			(*(volatile UINT *) (I2S_BASE + 0x08))
#define rI2CADD_L			(*(volatile UINT *) (I2S_BASE + 0x0A))
#define rI2CDS_H			(*(volatile UINT *) (I2S_BASE + 0x0C))                                                       
#define rI2CDS_L			(*(volatile UINT *) (I2S_BASE + 0x0E))                                                       


/********************************************* 
 *   SAIU(I2S) Register