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📄 t5_3.rpt

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_LC5_A4  = LCELL( _EQ011);
  _EQ011 = !_LC1_A5 &  _LC2_A6
         # !_LC1_A5 &  _LC2_A5
         # !_LC1_A5 & !_LC1_A6
         #  _LC2_A5 &  _LC2_A6
         #  _LC1_A6 &  _LC2_A6;

-- Node name is '|DELED:11|~264~1' from file "deled.tdf" line 25, column 28
-- Equation name is '_LC6_A1', type is buried 
-- synthesized logic cell 
_LC6_A1  = LCELL( _EQ012);
  _EQ012 = !_LC1_A5 & !_LC1_A6 & !_LC2_A5 & !_LC2_A6
         # !_LC1_A5 &  _LC1_A6 &  _LC2_A6
         # !_LC1_A5 &  _LC1_A6 &  _LC2_A5;

-- Node name is '|DELED:11|~264~2' from file "deled.tdf" line 25, column 28
-- Equation name is '_LC8_A1', type is buried 
-- synthesized logic cell 
_LC8_A1  = LCELL( _EQ013);
  _EQ013 = !_LC1_A5 & !_LC1_A6 &  _LC2_A6
         # !_LC1_A6 & !_LC2_A5 &  _LC2_A6
         # !_LC1_A5 &  _LC1_A6 & !_LC2_A5 & !_LC2_A6;

-- Node name is '|DELED:11|~264~3' from file "deled.tdf" line 25, column 28
-- Equation name is '_LC4_A2', type is buried 
-- synthesized logic cell 
_LC4_A2  = LCELL( _EQ014);
  _EQ014 = !_LC1_A5 &  _LC1_A6 &  _LC2_A5;

-- Node name is '|DELED:11|:264' from file "deled.tdf" line 25, column 28
-- Equation name is '_LC3_A1', type is buried 
_LC3_A1  = LCELL( _EQ015);
  _EQ015 =  _LC8_A1
         #  _LC1_A8
         #  _LC6_A1;

-- Node name is '|DELED:11|~266~1' from file "deled.tdf" line 25, column 30
-- Equation name is '_LC6_A2', type is buried 
-- synthesized logic cell 
_LC6_A2  = LCELL( _EQ016);
  _EQ016 =  _LC1_A5 & !_LC1_A6 &  _LC2_A5 & !_LC2_A6
         # !_LC1_A5 & !_LC1_A6 &  _LC2_A6
         #  _LC1_A5 & !_LC2_A5 &  _LC2_A6
         # !_LC1_A5 &  _LC1_A6 & !_LC2_A5 & !_LC2_A6;

-- Node name is '|DELED:11|~266~2' from file "deled.tdf" line 25, column 30
-- Equation name is '_LC1_A8', type is buried 
-- synthesized logic cell 
_LC1_A8  = LCELL( _EQ017);
  _EQ017 =  _LC1_A5 &  _LC1_A6 & !_LC2_A5 & !_LC2_A6
         #  _LC1_A5 &  _LC2_A5 &  _LC2_A6;

-- Node name is '|DELED:11|:266' from file "deled.tdf" line 25, column 30
-- Equation name is '_LC5_A2', type is buried 
_LC5_A2  = LCELL( _EQ018);
  _EQ018 =  _LC4_A2
         # !_LC1_A7
         #  _LC1_A8
         #  _LC6_A2;

-- Node name is '|SH8_4:8|:49' from file "sh8_4.tdf" line 10, column 8
-- Equation name is '_LC1_A5', type is buried 
_LC1_A5  = LCELL( _EQ019);
  _EQ019 =  _LC1_B14 & !_LC1_C13
         #  _LC1_C13 &  _LC3_A5;

-- Node name is '|SH8_4:8|:51' from file "sh8_4.tdf" line 10, column 8
-- Equation name is '_LC2_A5', type is buried 
!_LC2_A5 = _LC2_A5~NOT;
_LC2_A5~NOT = LCELL( _EQ020);
  _EQ020 =  _LC1_C13 & !_LC4_A5
         # !_LC1_A15 & !_LC1_C13
         # !_LC1_A15 & !_LC4_A5;

-- Node name is '|SH8_4:8|:53' from file "sh8_4.tdf" line 10, column 8
-- Equation name is '_LC1_A6', type is buried 
!_LC1_A6 = _LC1_A6~NOT;
_LC1_A6~NOT = LCELL( _EQ021);
  _EQ021 =  _LC1_C13 & !_LC5_A5
         # !_LC1_C13 & !_LC4_A6
         # !_LC4_A6 & !_LC5_A5;

-- Node name is '|SH8_4:8|:55' from file "sh8_4.tdf" line 10, column 8
-- Equation name is '_LC2_A6', type is buried 
!_LC2_A6 = _LC2_A6~NOT;
_LC2_A6~NOT = LCELL( _EQ022);
  _EQ022 = !_LC1_C13 & !_LC5_A6
         #  _LC1_C13 & !_LC6_A6
         # !_LC5_A6 & !_LC6_A6;

-- Node name is '|74161:4|f74161:sub|:9' = '|74161:4|f74161:sub|QA' 
-- Equation name is '_LC1_B14', type is buried 
_LC1_B14 = DFFE(!_LC1_B14, GLOBAL( CKCNT), GLOBAL( RESET),  VCC,  VCC);

-- Node name is '|74161:4|f74161:sub|:87' = '|74161:4|f74161:sub|QB' 
-- Equation name is '_LC1_A15', type is buried 
_LC1_A15 = DFFE( _EQ023, GLOBAL( CKCNT), GLOBAL( RESET),  VCC,  VCC);
  _EQ023 =  _LC1_A15 & !_LC1_B14
         # !_LC1_A15 &  _LC1_B14;

-- Node name is '|74161:4|f74161:sub|:99' = '|74161:4|f74161:sub|QC' 
-- Equation name is '_LC4_A6', type is buried 
_LC4_A6  = DFFE( _EQ024, GLOBAL( CKCNT), GLOBAL( RESET),  VCC,  VCC);
  _EQ024 = !_LC1_A15 &  _LC4_A6
         # !_LC1_B14 &  _LC4_A6
         #  _LC1_A15 &  _LC1_B14 & !_LC4_A6;

-- Node name is '|74161:4|f74161:sub|:110' = '|74161:4|f74161:sub|QD' 
-- Equation name is '_LC5_A6', type is buried 
_LC5_A6  = DFFE( _EQ025, GLOBAL( CKCNT), GLOBAL( RESET),  VCC,  VCC);
  _EQ025 = !_LC1_A15 &  _LC5_A6
         # !_LC1_B14 &  _LC5_A6
         # !_LC4_A6 &  _LC5_A6
         #  _LC1_A15 &  _LC1_B14 &  _LC4_A6 & !_LC5_A6;

-- Node name is '|74161:4|f74161:sub|:104' 
-- Equation name is '_LC3_A6', type is buried 
_LC3_A6  = LCELL( _EQ026);
  _EQ026 =  _LC1_A15 &  _LC1_B14 &  _LC4_A6 &  _LC5_A6;

-- Node name is '|74161:5|f74161:sub|:9' = '|74161:5|f74161:sub|QA' 
-- Equation name is '_LC3_A5', type is buried 
_LC3_A5  = DFFE( _EQ027, GLOBAL( CKCNT), GLOBAL( RESET),  VCC,  VCC);
  _EQ027 =  _LC3_A5 & !_LC3_A6
         # !_LC3_A5 &  _LC3_A6;

-- Node name is '|74161:5|f74161:sub|:87' = '|74161:5|f74161:sub|QB' 
-- Equation name is '_LC4_A5', type is buried 
_LC4_A5  = DFFE( _EQ028, GLOBAL( CKCNT), GLOBAL( RESET),  VCC,  VCC);
  _EQ028 = !_LC3_A5 &  _LC4_A5
         # !_LC3_A6 &  _LC4_A5
         #  _LC3_A5 &  _LC3_A6 & !_LC4_A5;

-- Node name is '|74161:5|f74161:sub|:99' = '|74161:5|f74161:sub|QC' 
-- Equation name is '_LC5_A5', type is buried 
_LC5_A5  = DFFE( _EQ029, GLOBAL( CKCNT), GLOBAL( RESET),  VCC,  VCC);
  _EQ029 = !_LC3_A5 &  _LC5_A5
         # !_LC3_A6 &  _LC5_A5
         # !_LC4_A5 &  _LC5_A5
         #  _LC3_A5 &  _LC3_A6 &  _LC4_A5 & !_LC5_A5;

-- Node name is '|74161:5|f74161:sub|:110' = '|74161:5|f74161:sub|QD' 
-- Equation name is '_LC6_A6', type is buried 
_LC6_A6  = DFFE( _EQ030, GLOBAL( CKCNT), GLOBAL( RESET),  VCC,  VCC);
  _EQ030 = !_LC6_A5 &  _LC6_A6
         # !_LC5_A5 &  _LC6_A6
         #  _LC5_A5 &  _LC6_A5 & !_LC6_A6;

-- Node name is '|74161:5|f74161:sub|:96' 
-- Equation name is '_LC6_A5', type is buried 
_LC6_A5  = LCELL( _EQ031);
  _EQ031 =  _LC3_A5 &  _LC3_A6 &  _LC4_A5;

-- Node name is ':9' 
-- Equation name is '_LC1_C13', type is buried 
_LC1_C13 = DFFE(!_LC1_C13, GLOBAL( CKDSP), GLOBAL( RESET),  VCC,  VCC);



Project Information                         c:\edatest\altera\test5\3\t5_3.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:02
   Partitioner                            00:00:01
   Fitter                                 00:00:04
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:10


Memory Allocated
-----------------

Peak memory allocated during compilation  = 8,732K

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