📄 t5_3.rpt
字号:
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\edatest\altera\test5\3\t5_3.rpt
t5_3
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 07 AND2 ! 0 4 0 4 |DELED:11|:58
- 1 - A 02 AND2 ! 0 4 0 1 |DELED:11|:132
- 3 - A 02 OR2 0 4 1 0 |DELED:11|:227
- 2 - A 02 AND2 s 0 3 0 1 |DELED:11|~229~1
- 1 - A 03 OR2 0 4 1 0 |DELED:11|:229
- 1 - A 01 OR2 s 0 4 0 1 |DELED:11|~245~1
- 4 - A 01 OR2 0 4 1 0 |DELED:11|:245
- 2 - A 01 OR2 s 0 4 0 1 |DELED:11|~260~1
- 7 - A 01 OR2 0 3 1 0 |DELED:11|:260
- 5 - A 01 OR2 s 0 4 0 1 |DELED:11|~262~1
- 5 - A 04 OR2 0 4 1 0 |DELED:11|:262
- 6 - A 01 OR2 s 0 4 0 3 |DELED:11|~264~1
- 8 - A 01 OR2 s 0 4 0 1 |DELED:11|~264~2
- 4 - A 02 AND2 s 0 3 0 1 |DELED:11|~264~3
- 3 - A 01 OR2 0 3 1 0 |DELED:11|:264
- 6 - A 02 OR2 s 0 4 0 2 |DELED:11|~266~1
- 1 - A 08 OR2 s 0 4 0 2 |DELED:11|~266~2
- 5 - A 02 OR2 0 4 1 0 |DELED:11|:266
- 1 - A 05 OR2 0 3 0 12 |SH8_4:8|:49
- 2 - A 05 OR2 ! 0 3 0 13 |SH8_4:8|:51
- 1 - A 06 OR2 ! 0 3 0 13 |SH8_4:8|:53
- 2 - A 06 OR2 ! 0 3 0 12 |SH8_4:8|:55
- 1 - C 13 DFFE + 0 0 1 4 :9
- 1 - B 14 DFFE + 0 0 0 5 |74161:4|f74161:sub|QA (|74161:4|f74161:sub|:9)
- 1 - A 15 DFFE + 0 1 0 4 |74161:4|f74161:sub|QB (|74161:4|f74161:sub|:87)
- 4 - A 06 DFFE + 0 2 0 3 |74161:4|f74161:sub|QC (|74161:4|f74161:sub|:99)
- 3 - A 06 AND2 0 4 0 4 |74161:4|f74161:sub|:104
- 5 - A 06 DFFE + 0 3 0 2 |74161:4|f74161:sub|QD (|74161:4|f74161:sub|:110)
- 3 - A 05 DFFE + 0 1 0 4 |74161:5|f74161:sub|QA (|74161:5|f74161:sub|:9)
- 4 - A 05 DFFE + 0 2 0 3 |74161:5|f74161:sub|QB (|74161:5|f74161:sub|:87)
- 6 - A 05 AND2 0 3 0 1 |74161:5|f74161:sub|:96
- 5 - A 05 DFFE + 0 3 0 2 |74161:5|f74161:sub|QC (|74161:5|f74161:sub|:99)
- 6 - A 06 DFFE + 0 2 0 1 |74161:5|f74161:sub|QD (|74161:5|f74161:sub|:110)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\edatest\altera\test5\3\t5_3.rpt
t5_3
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 13/ 48( 27%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\edatest\altera\test5\3\t5_3.rpt
t5_3
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 CKCNT
INPUT 1 CKDSP
Device-Specific Information: c:\edatest\altera\test5\3\t5_3.rpt
t5_3
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 RESET
Device-Specific Information: c:\edatest\altera\test5\3\t5_3.rpt
t5_3
** EQUATIONS **
CKCNT : INPUT;
CKDSP : INPUT;
RESET : INPUT;
-- Node name is 'A'
-- Equation name is 'A', type is output
A = _LC7_A1;
-- Node name is 'B'
-- Equation name is 'B', type is output
B = _LC3_A2;
-- Node name is 'C'
-- Equation name is 'C', type is output
C = _LC1_A3;
-- Node name is 'D'
-- Equation name is 'D', type is output
D = _LC4_A1;
-- Node name is 'E'
-- Equation name is 'E', type is output
E = _LC5_A4;
-- Node name is 'F'
-- Equation name is 'F', type is output
F = _LC3_A1;
-- Node name is 'G'
-- Equation name is 'G', type is output
G = _LC5_A2;
-- Node name is 'SEL0'
-- Equation name is 'SEL0', type is output
SEL0 = _LC1_C13;
-- Node name is '|DELED:11|:58' from file "deled.tdf" line 12, column 5
-- Equation name is '_LC1_A7', type is buried
!_LC1_A7 = _LC1_A7~NOT;
_LC1_A7~NOT = LCELL( _EQ001);
_EQ001 = !_LC1_A5 & !_LC1_A6 & _LC2_A5 & !_LC2_A6;
-- Node name is '|DELED:11|:132' from file "deled.tdf" line 17, column 5
-- Equation name is '_LC1_A2', type is buried
!_LC1_A2 = _LC1_A2~NOT;
_LC1_A2~NOT = LCELL( _EQ002);
_EQ002 = _LC1_A5 & _LC1_A6 & _LC2_A5 & !_LC2_A6;
-- Node name is '|DELED:11|:227' from file "deled.tdf" line 23, column 20
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = LCELL( _EQ003);
_EQ003 = !_LC1_A7
# !_LC1_A2
# _LC6_A2
# _LC2_A2;
-- Node name is '|DELED:11|~229~1' from file "deled.tdf" line 23, column 22
-- Equation name is '_LC2_A2', type is buried
-- synthesized logic cell
_LC2_A2 = LCELL( _EQ004);
_EQ004 = !_LC1_A6 & !_LC2_A5 & !_LC2_A6;
-- Node name is '|DELED:11|:229' from file "deled.tdf" line 23, column 22
-- Equation name is '_LC1_A3', type is buried
_LC1_A3 = LCELL( _EQ005);
_EQ005 = _LC1_A5 & !_LC1_A6 & _LC2_A5
# _LC1_A5 & _LC1_A6 & !_LC2_A5
# !_LC1_A6 & _LC2_A6
# _LC1_A6 & !_LC2_A6
# !_LC1_A5 & !_LC1_A6 & !_LC2_A5
# _LC1_A5 & !_LC2_A5 & !_LC2_A6;
-- Node name is '|DELED:11|~245~1' from file "deled.tdf" line 24, column 24
-- Equation name is '_LC1_A1', type is buried
-- synthesized logic cell
_LC1_A1 = LCELL( _EQ006);
_EQ006 = _LC1_A5 & _LC1_A6 & !_LC2_A5 & !_LC2_A6
# _LC1_A5 & !_LC1_A6 & _LC2_A5 & !_LC2_A6
# !_LC1_A6 & !_LC2_A5 & _LC2_A6;
-- Node name is '|DELED:11|:245' from file "deled.tdf" line 24, column 24
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = LCELL( _EQ007);
_EQ007 = _LC6_A1
# !_LC1_A7
# _LC5_A1
# _LC1_A1;
-- Node name is '|DELED:11|~260~1' from file "deled.tdf" line 25, column 18
-- Equation name is '_LC2_A1', type is buried
-- synthesized logic cell
_LC2_A1 = LCELL( _EQ008);
_EQ008 = _LC1_A5 & _LC2_A5 & !_LC2_A6
# _LC1_A5 & _LC1_A6 & !_LC2_A6
# !_LC1_A5 & !_LC1_A6 & _LC2_A6
# !_LC1_A6 & !_LC2_A5 & _LC2_A6
# _LC1_A5 & _LC1_A6 & _LC2_A5;
-- Node name is '|DELED:11|:260' from file "deled.tdf" line 25, column 18
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = LCELL( _EQ009);
_EQ009 = _LC2_A1
# _LC6_A1
# !_LC1_A7;
-- Node name is '|DELED:11|~262~1' from file "deled.tdf" line 25, column 26
-- Equation name is '_LC5_A1', type is buried
-- synthesized logic cell
_LC5_A1 = LCELL( _EQ010);
_EQ010 = _LC1_A5 & !_LC1_A6 & _LC2_A5 & _LC2_A6
# _LC1_A5 & _LC1_A6 & !_LC2_A5 & _LC2_A6;
-- Node name is '|DELED:11|:262' from file "deled.tdf" line 25, column 26
-- Equation name is '_LC5_A4', type is buried
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