📄 t5_1.rpt
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Device-Specific Information: c:\edatest\altera\test5\1\t5_1.rpt
t5_1
** CLOCK SIGNALS **
Type Fan-out Name
DFF 17 D0
DFF 17 D1
DFF 17 D2
INPUT 3 CKDSP
INPUT 1 CLK
Device-Specific Information: c:\edatest\altera\test5\1\t5_1.rpt
t5_1
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 7 RESET
Device-Specific Information: c:\edatest\altera\test5\1\t5_1.rpt
t5_1
** EQUATIONS **
CKDSP : INPUT;
CLK : INPUT;
RESET : INPUT;
-- Node name is 'A'
-- Equation name is 'A', type is output
A = _LC5_A6;
-- Node name is 'B'
-- Equation name is 'B', type is output
B = _LC3_A2;
-- Node name is 'C'
-- Equation name is 'C', type is output
C = _LC1_A2;
-- Node name is 'D'
-- Equation name is 'D', type is output
D = _LC6_A4;
-- Node name is ':1' = 'D0'
-- Equation name is 'D0', location is LC1_A12, type is buried.
D0 = DFFE(!D0, GLOBAL( CLK), GLOBAL( RESET), VCC, VCC);
-- Node name is ':3' = 'D1'
-- Equation name is 'D1', location is LC1_A9, type is buried.
D1 = DFFE(!D1, !D0, GLOBAL( RESET), VCC, VCC);
-- Node name is ':4' = 'D2'
-- Equation name is 'D2', location is LC1_A11, type is buried.
D2 = DFFE(!D2, !D1, GLOBAL( RESET), VCC, VCC);
-- Node name is ':5' = 'D3'
-- Equation name is 'D3', location is LC1_A10, type is buried.
D3 = DFFE(!D3, !D2, GLOBAL( RESET), VCC, VCC);
-- Node name is 'E'
-- Equation name is 'E', type is output
E = _LC3_A3;
-- Node name is 'F'
-- Equation name is 'F', type is output
F = _LC1_A7;
-- Node name is 'G'
-- Equation name is 'G', type is output
G = _LC5_A5;
-- Node name is 'SEL0'
-- Equation name is 'SEL0', type is output
SEL0 = _LC8_A1;
-- Node name is 'SEL1'
-- Equation name is 'SEL1', type is output
SEL1 = _LC1_A1;
-- Node name is 'SEL2'
-- Equation name is 'SEL2', type is output
SEL2 = _LC3_A1;
-- Node name is '|DELED:20|:58' from file "deled.tdf" line 12, column 5
-- Equation name is '_LC1_A8', type is buried
!_LC1_A8 = _LC1_A8~NOT;
_LC1_A8~NOT = LCELL( _EQ001);
_EQ001 = !D0 & D1 & !D2 & !D3;
-- Node name is '|DELED:20|:72' from file "deled.tdf" line 13, column 5
-- Equation name is '_LC1_A6', type is buried
!_LC1_A6 = _LC1_A6~NOT;
_LC1_A6~NOT = LCELL( _EQ002);
_EQ002 = D0 & D1 & !D2 & !D3;
-- Node name is '|DELED:20|:86' from file "deled.tdf" line 14, column 5
-- Equation name is '_LC1_A4', type is buried
!_LC1_A4 = _LC1_A4~NOT;
_LC1_A4~NOT = LCELL( _EQ003);
_EQ003 = !D0 & !D1 & D2 & !D3;
-- Node name is '|DELED:20|:132' from file "deled.tdf" line 17, column 5
-- Equation name is '_LC2_A6', type is buried
!_LC2_A6 = _LC2_A6~NOT;
_LC2_A6~NOT = LCELL( _EQ004);
_EQ004 = D0 & D1 & D2 & !D3;
-- Node name is '|DELED:20|:142' from file "deled.tdf" line 18, column 5
-- Equation name is '_LC2_A5', type is buried
!_LC2_A5 = _LC2_A5~NOT;
_LC2_A5~NOT = LCELL( _EQ005);
_EQ005 = !D0 & !D1 & !D2 & D3;
-- Node name is '|DELED:20|:178' from file "deled.tdf" line 20, column 5
-- Equation name is '_LC3_A5', type is buried
!_LC3_A5 = _LC3_A5~NOT;
_LC3_A5~NOT = LCELL( _EQ006);
_EQ006 = !D0 & D1 & !D2 & D3;
-- Node name is '|DELED:20|~227~1' from file "deled.tdf" line 23, column 20
-- Equation name is '_LC2_A2', type is buried
-- synthesized logic cell
_LC2_A2 = LCELL( _EQ007);
_EQ007 = D0 & D1 & !D2 & !D3
# D0 & !D1 & D3;
-- Node name is '|DELED:20|:227' from file "deled.tdf" line 23, column 20
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = LCELL( _EQ008);
_EQ008 = !_LC1_A4
# _LC4_A2
# _LC2_A2
# !_LC1_A8;
-- Node name is '|DELED:20|~229~1' from file "deled.tdf" line 23, column 22
-- Equation name is '_LC4_A2', type is buried
-- synthesized logic cell
_LC4_A2 = LCELL( _EQ009);
_EQ009 = !D0 & !D2 & D3
# !D0 & !D1 & !D2
# !D1 & !D2 & !D3
# D0 & D1 & D2 & !D3;
-- Node name is '|DELED:20|~229~2' from file "deled.tdf" line 23, column 22
-- Equation name is '_LC2_A3', type is buried
-- synthesized logic cell
_LC2_A3 = LCELL( _EQ010);
_EQ010 = D0 & !D1 & D3
# D0 & D1 & !D2
# D0 & !D2 & D3
# D0 & !D1 & D2
# !D0 & D1 & D2 & !D3;
-- Node name is '|DELED:20|:229' from file "deled.tdf" line 23, column 22
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = LCELL( _EQ011);
_EQ011 = _LC2_A3
# !_LC1_A4
# _LC4_A2;
-- Node name is '|DELED:20|:241' from file "deled.tdf" line 24, column 5
-- Equation name is '_LC4_A5', type is buried
!_LC4_A5 = _LC4_A5~NOT;
_LC4_A5~NOT = LCELL( _EQ012);
_EQ012 = !D0 & D1 & D2 & D3;
-- Node name is '|DELED:20|:245' from file "deled.tdf" line 24, column 24
-- Equation name is '_LC6_A4', type is buried
_LC6_A4 = LCELL( _EQ013);
_EQ013 = !D0 & !D1 & !D2
# D0 & D1 & !D2
# D0 & !D1 & D2
# !D0 & D1 & D2
# !D0 & !D2 & !D3
# !D1 & D3;
-- Node name is '|DELED:20|:258' from file "deled.tdf" line 25, column 5
-- Equation name is '_LC6_A5', type is buried
!_LC6_A5 = _LC6_A5~NOT;
_LC6_A5~NOT = LCELL( _EQ014);
_EQ014 = D0 & D1 & D2 & D3;
-- Node name is '|DELED:20|:260' from file "deled.tdf" line 25, column 18
-- Equation name is '_LC5_A6', type is buried
_LC5_A6 = LCELL( _EQ015);
_EQ015 = !_LC1_A8
# !_LC2_A6
# !_LC1_A6
# _LC3_A6;
-- Node name is '|DELED:20|:262' from file "deled.tdf" line 25, column 26
-- Equation name is '_LC3_A3', type is buried
_LC3_A3 = LCELL( _EQ016);
_EQ016 = !D0 & !D2
# D2 & D3
# !D0 & D1
# D1 & D3;
-- Node name is '|DELED:20|~264~1' from file "deled.tdf" line 25, column 28
-- Equation name is '_LC3_A6', type is buried
-- synthesized logic cell
_LC3_A6 = LCELL( _EQ017);
_EQ017 = D0 & !D1 & D2 & !D3
# !D1 & !D2 & D3
# !D0 & !D1 & !D2
# D1 & D2 & D3
# !D0 & D1 & D2
# !D0 & D3;
-- Node name is '|DELED:20|:264' from file "deled.tdf" line 25, column 28
-- Equation name is '_LC1_A7', type is buried
_LC1_A7 = LCELL( _EQ018);
_EQ018 = !D1 & D2 & !D3
# !D2 & D3
# !D0 & !D1 & !D3
# !D0 & !D1 & D2
# !D0 & D2 & !D3
# D1 & D3;
-- Node name is '|DELED:20|~266~1' from file "deled.tdf" line 25, column 30
-- Equation name is '_LC1_A5', type is buried
-- synthesized logic cell
_LC1_A5 = LCELL( _EQ019);
_EQ019 = !_LC4_A5
# _LC2_A3
# !_LC1_A8
# !_LC6_A5;
-- Node name is '|DELED:20|:266' from file "deled.tdf" line 25, column 30
-- Equation name is '_LC5_A5', type is buried
_LC5_A5 = LCELL( _EQ020);
_EQ020 = _LC1_A5
# !_LC3_A5
# !_LC2_A5
# !_LC1_A4;
-- Node name is '|74161:14|f74161:sub|:9' = '|74161:14|f74161:sub|QA'
-- Equation name is '_LC8_A1', type is buried
_LC8_A1 = DFFE(!_LC8_A1, GLOBAL( CKDSP), GLOBAL( RESET), VCC, VCC);
-- Node name is '|74161:14|f74161:sub|:87' = '|74161:14|f74161:sub|QB'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = DFFE( _EQ021, GLOBAL( CKDSP), GLOBAL( RESET), VCC, VCC);
_EQ021 = !_LC1_A1 & _LC8_A1
# _LC1_A1 & !_LC8_A1;
-- Node name is '|74161:14|f74161:sub|:99' = '|74161:14|f74161:sub|QC'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = DFFE( _EQ022, GLOBAL( CKDSP), GLOBAL( RESET), VCC, VCC);
_EQ022 = _LC3_A1 & !_LC8_A1
# !_LC1_A1 & _LC3_A1
# _LC1_A1 & !_LC3_A1 & _LC8_A1;
Project Information c:\edatest\altera\test5\1\t5_1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:02
Partitioner 00:00:01
Fitter 00:00:06
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:11
Memory Allocated
-----------------
Peak memory allocated during compilation = 8,800K
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