📄 t8.rpt
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_LC7_A9 = LCELL( _EQ015);
_EQ015 = count2 & count5 & count6 & count7;
-- Node name is '~229~2' from file "t8.tdf" line 25, column 8
-- Equation name is '~229~2', location is LC1_A9, type is buried.
-- synthesized logic cell
_LC1_A9 = LCELL( _EQ016);
_EQ016 = count3 & count4 & _LC2_A9 & _LC7_A9;
-- Node name is ':245' from file "t8.tdf" line 31, column 39
-- Equation name is '_LC1_A5', type is buried
_LC1_A5 = LCELL( _EQ017);
_EQ017 = count1
# count0
# count2;
-- Node name is ':250' from file "t8.tdf" line 31, column 39
-- Equation name is '_LC3_B2', type is buried
_LC3_B2 = LCELL( _EQ018);
_EQ018 = count3
# _LC1_A5;
-- Node name is ':256' from file "t8.tdf" line 31, column 39
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = LCELL( _EQ019);
_EQ019 = count3
# _LC1_A5
# count4;
-- Node name is ':261' from file "t8.tdf" line 31, column 39
-- Equation name is '_LC1_A10', type is buried
_LC1_A10 = LCELL( _EQ020);
_EQ020 = count3
# _LC1_A5
# count4
# count5;
-- Node name is '~308~1' from file "t8.tdf" line 32, column 21
-- Equation name is '~308~1', location is LC6_A9, type is buried.
-- synthesized logic cell
_LC6_A9 = LCELL( _EQ021);
_EQ021 = count3
# count2
# count7
# count1;
-- Node name is ':308' from file "t8.tdf" line 32, column 21
-- Equation name is '_LC5_A9', type is buried
!_LC5_A9 = _LC5_A9~NOT;
_LC5_A9~NOT = LCELL( _EQ022);
_EQ022 = _LC6_A9
# count5
# count6
# count4;
-- Node name is ':311' from file "t8.tdf" line 32, column 8
-- Equation name is '_LC3_A9', type is buried
_LC3_A9 = LCELL( _EQ023);
_EQ023 = !_LC5_A9 & !model0 & model1 & subadd;
-- Node name is ':315' from file "t8.tdf" line 38, column 7
-- Equation name is '_LC2_C8', type is buried
!_LC2_C8 = _LC2_C8~NOT;
_LC2_C8~NOT = LCELL( _EQ024);
_EQ024 = model0 & model1;
-- Node name is '~341~1' from file "t8.tdf" line 39, column 24
-- Equation name is '~341~1', location is LC2_A7, type is buried.
-- synthesized logic cell
_LC2_A7 = LCELL( _EQ025);
_EQ025 = !model0 & model1 & subadd
# model0 & !model1;
-- Node name is '~341~2' from file "t8.tdf" line 39, column 24
-- Equation name is '~341~2', location is LC2_A11, type is buried.
-- synthesized logic cell
_LC2_A11 = LCELL( _EQ026);
_EQ026 = !model0 & !subadd
# !model0 & !model1;
-- Node name is '~341~3' from file "t8.tdf" line 39, column 24
-- Equation name is '~341~3', location is LC1_A3, type is buried.
-- synthesized logic cell
_LC1_A3 = LCELL( _EQ027);
_EQ027 = count0 & !count1 & _LC2_A11
# !count0 & count1 & _LC2_A11
# !count0 & !count1 & _LC2_A7
# count0 & count1 & _LC2_A7;
-- Node name is '~344~1' from file "t8.tdf" line 39, column 24
-- Equation name is '~344~1', location is LC3_A1, type is buried.
-- synthesized logic cell
_LC3_A1 = LCELL( _EQ028);
_EQ028 = !count0 & !count1 & !count2 & _LC2_A7
# count1 & count2 & _LC2_A7
# count0 & count2 & _LC2_A7;
-- Node name is '~344~2' from file "t8.tdf" line 39, column 24
-- Equation name is '~344~2', location is LC4_A1, type is buried.
-- synthesized logic cell
_LC4_A1 = LCELL( _EQ029);
_EQ029 = !count1 & count2 & _LC2_A11
# !count0 & count2 & _LC2_A11
# count0 & count1 & !count2 & _LC2_A11;
-- Node name is '~347~1' from file "t8.tdf" line 39, column 24
-- Equation name is '~347~1', location is LC5_A1, type is buried.
-- synthesized logic cell
_LC5_A1 = LCELL( _EQ030);
_EQ030 = count3 & _LC2_A11 & !_LC3_A13
# !count3 & _LC2_A11 & _LC3_A13
# count3 & !_LC2_C8;
-- Node name is '~350~1' from file "t8.tdf" line 39, column 24
-- Equation name is '~350~1', location is LC2_A1, type is buried.
-- synthesized logic cell
_LC2_A1 = LCELL( _EQ031);
_EQ031 = count4 & _LC2_A11 & !_LC6_A1
# !count4 & _LC2_A11 & _LC6_A1
# count4 & !_LC2_C8;
-- Node name is '~354~1' from file "t8.tdf" line 39, column 24
-- Equation name is '~354~1', location is LC1_A4, type is buried.
-- synthesized logic cell
_LC1_A4 = LCELL( _EQ032);
_EQ032 = count5 & _LC2_A11 & !_LC5_A4
# !count5 & _LC2_A11 & _LC5_A4
# !count5 & !_LC2_C8;
-- Node name is '~357~1' from file "t8.tdf" line 39, column 24
-- Equation name is '~357~1', location is LC2_A4, type is buried.
-- synthesized logic cell
_LC2_A4 = LCELL( _EQ033);
_EQ033 = !count5 & count6 & _LC2_A11
# count6 & _LC2_A11 & !_LC5_A4
# count5 & !count6 & _LC2_A11 & _LC5_A4;
-- Node name is '~357~2' from file "t8.tdf" line 39, column 24
-- Equation name is '~357~2', location is LC2_A3, type is buried.
-- synthesized logic cell
_LC2_A3 = LCELL( _EQ034);
_EQ034 = _LC2_A4
# !count5 & count6 & !_LC2_C8
# count5 & !count6 & !_LC2_C8;
-- Node name is ':359' from file "t8.tdf" line 39, column 24
-- Equation name is '_LC4_A4', type is buried
_LC4_A4 = LCELL( _EQ035);
_EQ035 = !count6 & count7 & !_LC2_C8
# !count5 & count7 & !_LC2_C8
# count5 & count6 & !count7 & !_LC2_C8;
-- Node name is '~360~1' from file "t8.tdf" line 39, column 24
-- Equation name is '~360~1', location is LC7_A4, type is buried.
-- synthesized logic cell
_LC7_A4 = LCELL( _EQ036);
_EQ036 = !count6 & !count7 & !_LC1_A10 & _LC2_A7
# count6 & count7 & _LC2_A7
# count7 & _LC1_A10 & _LC2_A7;
Project Information c:\edatest\altera\test8\t8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:01
Fitter 00:00:04
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:08
Memory Allocated
-----------------
Peak memory allocated during compilation = 9,408K
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