📄 read.rpt
字号:
39 - - - 11 OUTPUT 0 1 0 0 LOUT2
38 - - - 10 OUTPUT 0 1 0 0 LOUT3
9 - - - 02 OUTPUT 0 1 0 0 LOUT4
3 - - - 12 OUTPUT 0 1 0 0 LOUT5
35 - - - 06 OUTPUT 0 1 0 0 LOUT6
11 - - - 01 OUTPUT 0 1 0 0 LOUT7
18 - - A -- OUTPUT 0 1 0 0 RDn
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\edatest\altera\test7\read.rpt
read
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 01 DFFE + 0 2 1 2 |addr1:12|:34
- 8 - B 01 DFFE + 0 2 1 2 |addr1:12|:35
- 3 - B 01 DFFE + 0 3 1 1 |addr1:12|:36
- 5 - B 01 DFFE + 0 2 1 2 |addr1:12|:37
- 7 - B 01 DFFE + 0 1 1 3 |addr1:12|:38
- 4 - B 01 OR2 ! 0 3 0 3 |addr1:12|:43
- 2 - B 01 OR2 ! 0 3 0 3 |addr1:12|:46
- 7 - B 02 DFFE + 0 3 1 0 |addr:3|:33
- 3 - B 02 DFFE + 0 2 1 1 |addr:3|:34
- 5 - B 02 DFFE + 0 1 1 2 |addr:3|:35
- 1 - B 02 DFFE + 0 0 1 3 |addr:3|:36
- 3 - A 05 DFFE + 0 2 0 5 |sequ:1|count0
- 4 - A 05 DFFE + 0 2 0 6 |sequ:1|count1
- 6 - A 05 DFFE + 0 2 0 6 |sequ:1|count2
- 5 - A 05 DFFE + ! 0 3 1 0 |sequ:1|:55
- 7 - A 05 DFFE + 0 2 1 0 |sequ:1|:56
- 2 - A 06 DFFE 1 1 1 0 |sequ:1|:57
- 1 - A 07 DFFE 1 1 1 0 |sequ:1|:58
- 4 - A 03 DFFE 1 1 1 0 |sequ:1|:59
- 3 - A 04 DFFE 1 1 1 0 |sequ:1|:60
- 2 - A 03 DFFE 1 1 1 0 |sequ:1|:61
- 2 - A 04 DFFE 1 1 1 0 |sequ:1|:62
- 1 - A 04 DFFE 1 1 1 0 |sequ:1|:63
- 1 - A 03 DFFE 1 1 1 0 |sequ:1|:64
- 1 - A 01 DFFE 1 1 1 0 |sequ:1|:65
- 1 - A 06 DFFE 1 1 1 0 |sequ:1|:66
- 1 - A 12 DFFE 1 1 1 0 |sequ:1|:67
- 1 - A 02 DFFE 1 1 1 0 |sequ:1|:68
- 1 - A 10 DFFE 1 1 1 0 |sequ:1|:69
- 1 - A 11 DFFE 1 1 1 0 |sequ:1|:70
- 1 - A 09 DFFE 1 1 1 0 |sequ:1|:71
- 1 - A 08 DFFE 1 1 1 0 |sequ:1|:72
- 2 - A 05 OR2 0 3 0 8 |sequ:1|:113
- 1 - A 05 AND2 ! 0 3 0 8 |sequ:1|:185
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\edatest\altera\test7\read.rpt
read
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 5/ 48( 10%) 0/ 48( 0%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
B: 4/ 96( 4%) 5/ 48( 10%) 0/ 48( 0%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 0/ 96( 0%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\edatest\altera\test7\read.rpt
read
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 CKDSP
LCELL 8 |sequ:1|:113
LCELL 8 |sequ:1|:185
INPUT 5 CLK
INPUT 5 HZSEL
Device-Specific Information: c:\edatest\altera\test7\read.rpt
read
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 CKDSP
INPUT 9 RESET
Device-Specific Information: c:\edatest\altera\test7\read.rpt
read
** EQUATIONS **
CKDSP : INPUT;
CLK : INPUT;
DATA0 : INPUT;
DATA1 : INPUT;
DATA2 : INPUT;
DATA3 : INPUT;
DATA4 : INPUT;
DATA5 : INPUT;
DATA6 : INPUT;
DATA7 : INPUT;
HZSEL : INPUT;
RESET : INPUT;
-- Node name is 'AD0'
-- Equation name is 'AD0', type is output
AD0 = _LC7_A5;
-- Node name is 'AD1'
-- Equation name is 'AD1', type is output
AD1 = _LC1_B2;
-- Node name is 'AD2'
-- Equation name is 'AD2', type is output
AD2 = _LC5_B2;
-- Node name is 'AD3'
-- Equation name is 'AD3', type is output
AD3 = _LC3_B2;
-- Node name is 'AD4'
-- Equation name is 'AD4', type is output
AD4 = _LC7_B2;
-- Node name is 'AD5'
-- Equation name is 'AD5', type is output
AD5 = _LC7_B1;
-- Node name is 'AD6'
-- Equation name is 'AD6', type is output
AD6 = _LC5_B1;
-- Node name is 'AD7'
-- Equation name is 'AD7', type is output
AD7 = _LC3_B1;
-- Node name is 'AD8'
-- Equation name is 'AD8', type is output
AD8 = _LC8_B1;
-- Node name is 'AD9'
-- Equation name is 'AD9', type is output
AD9 = _LC1_B1;
-- Node name is 'HOUT0'
-- Equation name is 'HOUT0', type is output
HOUT0 = _LC1_A3;
-- Node name is 'HOUT1'
-- Equation name is 'HOUT1', type is output
HOUT1 = _LC1_A4;
-- Node name is 'HOUT2'
-- Equation name is 'HOUT2', type is output
HOUT2 = _LC2_A4;
-- Node name is 'HOUT3'
-- Equation name is 'HOUT3', type is output
HOUT3 = _LC2_A3;
-- Node name is 'HOUT4'
-- Equation name is 'HOUT4', type is output
HOUT4 = _LC3_A4;
-- Node name is 'HOUT5'
-- Equation name is 'HOUT5', type is output
HOUT5 = _LC4_A3;
-- Node name is 'HOUT6'
-- Equation name is 'HOUT6', type is output
HOUT6 = _LC1_A7;
-- Node name is 'HOUT7'
-- Equation name is 'HOUT7', type is output
HOUT7 = _LC2_A6;
-- Node name is 'LOUT0'
-- Equation name is 'LOUT0', type is output
LOUT0 = _LC1_A8;
-- Node name is 'LOUT1'
-- Equation name is 'LOUT1', type is output
LOUT1 = _LC1_A9;
-- Node name is 'LOUT2'
-- Equation name is 'LOUT2', type is output
LOUT2 = _LC1_A11;
-- Node name is 'LOUT3'
-- Equation name is 'LOUT3', type is output
LOUT3 = _LC1_A10;
-- Node name is 'LOUT4'
-- Equation name is 'LOUT4', type is output
LOUT4 = _LC1_A2;
-- Node name is 'LOUT5'
-- Equation name is 'LOUT5', type is output
LOUT5 = _LC1_A12;
-- Node name is 'LOUT6'
-- Equation name is 'LOUT6', type is output
LOUT6 = _LC1_A6;
-- Node name is 'LOUT7'
-- Equation name is 'LOUT7', type is output
LOUT7 = _LC1_A1;
-- Node name is 'RDn'
-- Equation name is 'RDn', type is output
RDn = _LC5_A5;
-- Node name is '|addr1:12|:34' from file "addr1.tdf" line 8, column 6
-- Equation name is '_LC1_B1', type is buried
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