📄 addr1.rpt
字号:
- 3 - A 01 DFFE + 0 2 1 2 :37
- 1 - A 01 DFFE + 0 1 1 3 :38
- 2 - A 01 OR2 ! 0 3 0 3 :43
- 6 - A 01 OR2 ! 0 3 0 3 :46
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\edatest\altera\test7\addr1.rpt
addr1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\edatest\altera\test7\addr1.rpt
addr1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 hzsel
Device-Specific Information: c:\edatest\altera\test7\addr1.rpt
addr1
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 5 reset
Device-Specific Information: c:\edatest\altera\test7\addr1.rpt
addr1
** EQUATIONS **
hzsel : INPUT;
reset : INPUT;
-- Node name is 'ad5' from file "addr1.tdf" line 8, column 6
-- Equation name is 'ad5', type is output
ad5 = _LC1_A1;
-- Node name is 'ad6' from file "addr1.tdf" line 8, column 6
-- Equation name is 'ad6', type is output
ad6 = _LC3_A1;
-- Node name is 'ad7' from file "addr1.tdf" line 8, column 6
-- Equation name is 'ad7', type is output
ad7 = _LC5_A1;
-- Node name is 'ad8' from file "addr1.tdf" line 8, column 6
-- Equation name is 'ad8', type is output
ad8 = _LC7_A1;
-- Node name is 'ad9' from file "addr1.tdf" line 8, column 6
-- Equation name is 'ad9', type is output
ad9 = _LC4_A1;
-- Node name is ':34' from file "addr1.tdf" line 8, column 6
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = DFFE( _EQ001, GLOBAL( hzsel), GLOBAL( reset), VCC, VCC);
_EQ001 = _LC2_A1 & !_LC4_A1 & _LC7_A1
# !_LC2_A1 & _LC4_A1 & !_LC7_A1;
-- Node name is ':35' from file "addr1.tdf" line 8, column 6
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = DFFE( _EQ002, GLOBAL( hzsel), GLOBAL( reset), VCC, VCC);
_EQ002 = !_LC2_A1 & !_LC4_A1 & _LC7_A1
# _LC2_A1 & !_LC4_A1 & !_LC7_A1;
-- Node name is ':36' from file "addr1.tdf" line 8, column 6
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = DFFE( _EQ003, GLOBAL( hzsel), GLOBAL( reset), VCC, VCC);
_EQ003 = !_LC3_A1 & _LC5_A1 & !_LC6_A1
# !_LC1_A1 & _LC5_A1 & !_LC6_A1
# _LC1_A1 & _LC3_A1 & !_LC5_A1 & !_LC6_A1;
-- Node name is ':37' from file "addr1.tdf" line 8, column 6
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = DFFE( _EQ004, GLOBAL( hzsel), GLOBAL( reset), VCC, VCC);
_EQ004 = !_LC1_A1 & _LC3_A1 & !_LC6_A1
# _LC1_A1 & !_LC3_A1 & !_LC6_A1;
-- Node name is ':38' from file "addr1.tdf" line 8, column 6
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = DFFE( _EQ005, GLOBAL( hzsel), GLOBAL( reset), VCC, VCC);
_EQ005 = !_LC1_A1 & !_LC6_A1;
-- Node name is ':43' from file "addr1.tdf" line 13, column 13
-- Equation name is '_LC2_A1', type is buried
!_LC2_A1 = _LC2_A1~NOT;
_LC2_A1~NOT = LCELL( _EQ006);
_EQ006 = !_LC5_A1
# !_LC3_A1
# !_LC1_A1;
-- Node name is ':46' from file "addr1.tdf" line 13, column 13
-- Equation name is '_LC6_A1', type is buried
!_LC6_A1 = _LC6_A1~NOT;
_LC6_A1~NOT = LCELL( _EQ007);
_EQ007 = !_LC4_A1
# !_LC2_A1 & !_LC7_A1;
Project Information c:\edatest\altera\test7\addr1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 10,104K
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