70641.rpt

eda技术的相关资料

-- Equation name is 'E_IN', type is output 
E_IN     =  _LC4_C20;

-- Node name is 'F_IN' 
-- Equation name is 'F_IN', type is output 
F_IN     =  _LC5_C18;

-- Node name is 'G_IN' 
-- Equation name is 'G_IN', type is output 
G_IN     =  _LC6_C20;

-- Node name is 'INT0' 
-- Equation name is 'INT0', type is output 
INT0     =  _LC4_A22;

-- Node name is 'P10~1' 
-- Equation name is 'P10~1', location is LC4_A5, type is buried.
-- synthesized logic cell 
_LC4_A5  = LCELL( k1);

-- Node name is 'P10' 
-- Equation name is 'P10', type is output 
P10      =  _LC4_A5;

-- Node name is 'P11~1' 
-- Equation name is 'P11~1', location is LC4_A8, type is buried.
-- synthesized logic cell 
_LC4_A8  = LCELL( K2);

-- Node name is 'P11' 
-- Equation name is 'P11', type is output 
P11      =  _LC4_A8;

-- Node name is 'P12~1' 
-- Equation name is 'P12~1', location is LC4_A10, type is buried.
-- synthesized logic cell 
_LC4_A10 = LCELL( K3);

-- Node name is 'P12' 
-- Equation name is 'P12', type is output 
P12      =  _LC4_A10;

-- Node name is 'P13~1' 
-- Equation name is 'P13~1', location is LC4_A9, type is buried.
-- synthesized logic cell 
_LC4_A9  = LCELL( K4);

-- Node name is 'P13' 
-- Equation name is 'P13', type is output 
P13      =  _LC4_A9;

-- Node name is 'P14~1' 
-- Equation name is 'P14~1', location is LC1_A11, type is buried.
-- synthesized logic cell 
_LC1_A11 = LCELL( K5);

-- Node name is 'P14' 
-- Equation name is 'P14', type is output 
P14      =  _LC1_A11;

-- Node name is 'P15~1' 
-- Equation name is 'P15~1', location is LC1_A14, type is buried.
-- synthesized logic cell 
_LC1_A14 = LCELL( K6);

-- Node name is 'P15' 
-- Equation name is 'P15', type is output 
P15      =  _LC1_A14;

-- Node name is 'P16~1' 
-- Equation name is 'P16~1', location is LC1_A15, type is buried.
-- synthesized logic cell 
_LC1_A15 = LCELL( K7);

-- Node name is 'P16' 
-- Equation name is 'P16', type is output 
P16      =  _LC1_A15;

-- Node name is 'P17~1' 
-- Equation name is 'P17~1', location is LC7_A16, type is buried.
-- synthesized logic cell 
_LC7_A16 = LCELL( K8);

-- Node name is 'P17' 
-- Equation name is 'P17', type is output 
P17      =  _LC7_A16;

-- Node name is '|7402:86|:4' = '|7402:86|1' 
-- Equation name is '_LC3_C18', type is buried 
_LC3_C18 = LCELL( _EQ001);
  _EQ001 = !p23 & !wr;

-- Node name is '|7402:87|:4' = '|7402:87|1' 
-- Equation name is '_LC4_C18', type is buried 
_LC4_C18 = LCELL( _EQ002);
  _EQ002 = !p21 & !wr;

-- Node name is '|74273:22|:19' = '|74273:22|Q1' 
-- Equation name is '_LC3_C20', type is buried 
_LC3_C20 = DFFE( D0,  _LC3_C18,  VCC_R,  VCC,  VCC);

-- Node name is '|74273:22|:18' = '|74273:22|Q2' 
-- Equation name is '_LC8_C18', type is buried 
_LC8_C18 = DFFE( D1,  _LC3_C18,  VCC_R,  VCC,  VCC);

-- Node name is '|74273:22|:17' = '|74273:22|Q3' 
-- Equation name is '_LC7_C18', type is buried 
_LC7_C18 = DFFE( D2,  _LC3_C18,  VCC_R,  VCC,  VCC);

-- Node name is '|74273:25|:19' = '|74273:25|Q1' 
-- Equation name is '_LC5_C20', type is buried 
_LC5_C20 = DFFE( D0,  _LC4_C18,  VCC_R,  VCC,  VCC);

-- Node name is '|74273:25|:18' = '|74273:25|Q2' 
-- Equation name is '_LC6_C18', type is buried 
_LC6_C18 = DFFE( D1,  _LC4_C18,  VCC_R,  VCC,  VCC);

-- Node name is '|74273:25|:17' = '|74273:25|Q3' 
-- Equation name is '_LC1_C18', type is buried 
_LC1_C18 = DFFE( D2,  _LC4_C18,  VCC_R,  VCC,  VCC);

-- Node name is '|74273:25|:16' = '|74273:25|Q4' 
-- Equation name is '_LC2_C18', type is buried 
_LC2_C18 = DFFE( D3,  _LC4_C18,  VCC_R,  VCC,  VCC);

-- Node name is '|74273:25|:15' = '|74273:25|Q5' 
-- Equation name is '_LC4_C20', type is buried 
_LC4_C20 = DFFE( D4,  _LC4_C18,  VCC_R,  VCC,  VCC);

-- Node name is '|74273:25|:14' = '|74273:25|Q6' 
-- Equation name is '_LC5_C18', type is buried 
_LC5_C18 = DFFE( D5,  _LC4_C18,  VCC_R,  VCC,  VCC);

-- Node name is '|74273:25|:13' = '|74273:25|Q7' 
-- Equation name is '_LC6_C20', type is buried 
_LC6_C20 = DFFE( D6,  _LC4_C18,  VCC_R,  VCC,  VCC);

-- Node name is '~204~1' 
-- Equation name is '~204~1', location is LC1_A22, type is buried.
-- synthesized logic cell 
_LC1_A22 = LCELL( _EQ003);
  _EQ003 =  K6 &  K7 &  K8;

-- Node name is '~204~2' 
-- Equation name is '~204~2', location is LC2_A22, type is buried.
-- synthesized logic cell 
_LC2_A22 = LCELL( _EQ004);
  _EQ004 =  k1 &  K3 &  K4;

-- Node name is ':204' 
-- Equation name is '_LC4_A22', type is buried 
_LC4_A22 = LCELL( _EQ005);
  _EQ005 =  K2 &  K5 &  _LC1_A22 &  _LC2_A22;



Project Information                                 e:\altera\test10\70641.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = on
   Rules                                  = EPLD Rules


Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:03
   Fitter                                 00:00:08
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:01
   Design Doctor                          00:00:00
   --------------------------             --------
   Total Time                             00:00:14


Memory Allocated
-----------------

Peak memory allocated during compilation  = 12,446K