📄 70641.rpt
字号:
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 1 0 0 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 3 0 0 11/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 4 0 0 0 0 12/0
Total: 0 0 0 0 1 0 0 1 1 1 1 0 0 0 1 1 1 0 8 0 4 0 3 0 0 23/0
Device-Specific Information: e:\altera\test10\70641.rpt
70641
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
11 - - - 01 INPUT 0 0 0 2 D0
10 - - - 01 INPUT 0 0 0 2 D1
9 - - - 02 INPUT 0 0 0 2 D2
8 - - - 03 INPUT 0 0 0 1 D3
7 - - - 03 INPUT 0 0 0 1 D4
6 - - - 04 INPUT 0 0 0 1 D5
5 - - - 05 INPUT 0 0 0 1 D6
84 - - - -- INPUT 0 0 0 0 D7
81 - - - 22 INPUT 0 0 0 2 k1
80 - - - 23 INPUT 0 0 0 2 K2
79 - - - 24 INPUT 0 0 0 2 K3
78 - - - 24 INPUT 0 0 0 2 K4
73 - - A -- INPUT 0 0 0 2 K5
72 - - A -- INPUT 0 0 0 2 K6
71 - - A -- INPUT 0 0 0 2 K7
70 - - A -- INPUT 0 0 0 2 K8
69 - - A -- INPUT 0 0 0 1 p21
67 - - B -- INPUT 0 0 0 1 p23
1 - - - -- INPUT 0 0 0 10 VCC_R
66 - - B -- INPUT 0 0 0 2 wr
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\altera\test10\70641.rpt
70641
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
65 - - B -- OUTPUT 0 1 0 0 A_IN
64 - - B -- OUTPUT 0 1 0 0 B_IN
52 - - - 19 OUTPUT 0 1 0 0 BIT_SEL0
51 - - - 18 OUTPUT 0 1 0 0 BIT_SEL1
50 - - - 17 OUTPUT 0 1 0 0 BIT_SEL2
62 - - C -- OUTPUT 0 1 0 0 C_IN
61 - - C -- OUTPUT 0 1 0 0 D_IN
60 - - C -- OUTPUT 0 1 0 0 E_IN
59 - - C -- OUTPUT 0 1 0 0 F_IN
58 - - C -- OUTPUT 0 1 0 0 G_IN
54 - - - 21 OUTPUT 0 1 0 0 INT0
35 - - - 06 OUTPUT 0 1 0 0 P10
36 - - - 07 OUTPUT 0 1 0 0 P11
37 - - - 09 OUTPUT 0 1 0 0 P12
38 - - - 10 OUTPUT 0 1 0 0 P13
39 - - - 11 OUTPUT 0 1 0 0 P14
47 - - - 14 OUTPUT 0 1 0 0 P15
48 - - - 15 OUTPUT 0 1 0 0 P16
49 - - - 16 OUTPUT 0 1 0 0 P17
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\altera\test10\70641.rpt
70641
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 05 LCELL s 1 0 1 0 P10~1
- 4 - A 08 LCELL s 1 0 1 0 P11~1
- 4 - A 10 LCELL s 1 0 1 0 P12~1
- 4 - A 09 LCELL s 1 0 1 0 P13~1
- 1 - A 11 LCELL s 1 0 1 0 P14~1
- 1 - A 14 LCELL s 1 0 1 0 P15~1
- 1 - A 15 LCELL s 1 0 1 0 P16~1
- 7 - A 16 LCELL s 1 0 1 0 P17~1
- 1 - A 22 AND2 s 3 0 0 1 ~204~1
- 2 - A 22 AND2 s 3 0 0 1 ~204~2
- 4 - A 22 AND2 2 2 1 0 :204
- 3 - C 18 AND2 2 0 0 3 |7402:86|1 (|7402:86|:4)
- 4 - C 18 AND2 2 0 0 7 |7402:87|1 (|7402:87|:4)
- 7 - C 18 DFFE 2 1 1 0 |74273:22|Q3 (|74273:22|:17)
- 8 - C 18 DFFE 2 1 1 0 |74273:22|Q2 (|74273:22|:18)
- 3 - C 20 DFFE 2 1 1 0 |74273:22|Q1 (|74273:22|:19)
- 6 - C 20 DFFE 2 1 1 0 |74273:25|Q7 (|74273:25|:13)
- 5 - C 18 DFFE 2 1 1 0 |74273:25|Q6 (|74273:25|:14)
- 4 - C 20 DFFE 2 1 1 0 |74273:25|Q5 (|74273:25|:15)
- 2 - C 18 DFFE 2 1 1 0 |74273:25|Q4 (|74273:25|:16)
- 1 - C 18 DFFE 2 1 1 0 |74273:25|Q3 (|74273:25|:17)
- 6 - C 18 DFFE 2 1 1 0 |74273:25|Q2 (|74273:25|:18)
- 5 - C 20 DFFE 2 1 1 0 |74273:25|Q1 (|74273:25|:19)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\altera\test10\70641.rpt
70641
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 9/ 96( 9%) 0/ 48( 0%) 0/ 48( 0%) 5/16( 31%) 0/16( 0%) 0/16( 0%)
B: 2/ 96( 2%) 0/ 48( 0%) 2/ 48( 4%) 2/16( 12%) 2/16( 12%) 0/16( 0%)
C: 9/ 96( 9%) 0/ 48( 0%) 8/ 48( 16%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 3/24( 12%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\altera\test10\70641.rpt
70641
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 7 |7402:87|1
LCELL 3 |7402:86|1
Device-Specific Information: e:\altera\test10\70641.rpt
70641
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 10 VCC_R
Device-Specific Information: e:\altera\test10\70641.rpt
70641
** EQUATIONS **
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
D4 : INPUT;
D5 : INPUT;
D6 : INPUT;
D7 : INPUT;
k1 : INPUT;
K2 : INPUT;
K3 : INPUT;
K4 : INPUT;
K5 : INPUT;
K6 : INPUT;
K7 : INPUT;
K8 : INPUT;
p21 : INPUT;
p23 : INPUT;
VCC_R : INPUT;
wr : INPUT;
-- Node name is 'A_IN'
-- Equation name is 'A_IN', type is output
A_IN = _LC5_C20;
-- Node name is 'B_IN'
-- Equation name is 'B_IN', type is output
B_IN = _LC6_C18;
-- Node name is 'BIT_SEL0'
-- Equation name is 'BIT_SEL0', type is output
BIT_SEL0 = _LC3_C20;
-- Node name is 'BIT_SEL1'
-- Equation name is 'BIT_SEL1', type is output
BIT_SEL1 = _LC8_C18;
-- Node name is 'BIT_SEL2'
-- Equation name is 'BIT_SEL2', type is output
BIT_SEL2 = _LC7_C18;
-- Node name is 'C_IN'
-- Equation name is 'C_IN', type is output
C_IN = _LC1_C18;
-- Node name is 'D_IN'
-- Equation name is 'D_IN', type is output
D_IN = _LC2_C18;
-- Node name is 'E_IN'
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -