📄 t4_1.rpt
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EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\edatest\altera\test4\1\t4_1.rpt
t4_1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 CLK
Device-Specific Information: c:\edatest\altera\test4\1\t4_1.rpt
t4_1
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 3 RESET
Device-Specific Information: c:\edatest\altera\test4\1\t4_1.rpt
t4_1
** EQUATIONS **
CLK : INPUT;
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
RESET : INPUT;
-- Node name is 'A'
-- Equation name is 'A', type is output
A = _LC1_B5;
-- Node name is 'B'
-- Equation name is 'B', type is output
B = _LC2_B2;
-- Node name is 'C'
-- Equation name is 'C', type is output
C = _LC1_B4;
-- Node name is 'D'
-- Equation name is 'D', type is output
D = _LC2_B3;
-- Node name is 'E'
-- Equation name is 'E', type is output
E = _LC8_B7;
-- Node name is 'F'
-- Equation name is 'F', type is output
F = _LC3_B6;
-- Node name is 'G'
-- Equation name is 'G', type is output
G = _LC5_B2;
-- Node name is 'SEL0'
-- Equation name is 'SEL0', type is output
SEL0 = _LC3_A1;
-- Node name is 'SEL1'
-- Equation name is 'SEL1', type is output
SEL1 = _LC5_A1;
-- Node name is 'SEL2'
-- Equation name is 'SEL2', type is output
SEL2 = _LC1_A1;
-- Node name is '|DELED:1|:58' from file "deled.tdf" line 12, column 5
-- Equation name is '_LC3_B2', type is buried
!_LC3_B2 = _LC3_B2~NOT;
_LC3_B2~NOT = LCELL( _EQ001);
_EQ001 = !D0 & D1 & !D2 & !D3;
-- Node name is '|DELED:1|:227' from file "deled.tdf" line 23, column 20
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = LCELL( _EQ002);
_EQ002 = !_LC3_B2
# _LC7_B2
# _LC4_B2;
-- Node name is '|DELED:1|~229~1' from file "deled.tdf" line 23, column 22
-- Equation name is '_LC4_B2', type is buried
-- synthesized logic cell
_LC4_B2 = LCELL( _EQ003);
_EQ003 = D0 & D1 & D2 & !D3
# !D1 & !D2 & !D3;
-- Node name is '|DELED:1|:229' from file "deled.tdf" line 23, column 22
-- Equation name is '_LC1_B4', type is buried
_LC1_B4 = LCELL( _EQ004);
_EQ004 = !D2 & D3
# D0 & D1 & !D2
# D0 & !D1 & D2
# D2 & !D3
# !D1 & !D3;
-- Node name is '|DELED:1|~245~1' from file "deled.tdf" line 24, column 24
-- Equation name is '_LC3_B3', type is buried
-- synthesized logic cell
_LC3_B3 = LCELL( _EQ005);
_EQ005 = D0 & !D1 & D2 & !D3
# D0 & D1 & !D2 & !D3;
-- Node name is '|DELED:1|~245~2' from file "deled.tdf" line 24, column 24
-- Equation name is '_LC4_B3', type is buried
-- synthesized logic cell
_LC4_B3 = LCELL( _EQ006);
_EQ006 = !D1 & !D2 & D3;
-- Node name is '|DELED:1|:245' from file "deled.tdf" line 24, column 24
-- Equation name is '_LC2_B3', type is buried
_LC2_B3 = LCELL( _EQ007);
_EQ007 = _LC1_B3
# _LC3_B3
# _LC4_B3;
-- Node name is '|DELED:1|:260' from file "deled.tdf" line 25, column 18
-- Equation name is '_LC1_B5', type is buried
_LC1_B5 = LCELL( _EQ008);
_EQ008 = !D0 & !D2
# D0 & D2 & !D3
# D1 & !D3
# !D0 & D1
# !D0 & D3
# !D1 & !D2 & D3
# D1 & D2;
-- Node name is '|DELED:1|~262~1' from file "deled.tdf" line 25, column 26
-- Equation name is '_LC1_B3', type is buried
-- synthesized logic cell
_LC1_B3 = LCELL( _EQ009);
_EQ009 = !D0 & D1 & D2
# !D1 & D2 & D3
# !D0 & !D2 & !D3
# !D0 & D1 & !D3
# D0 & D1 & !D2 & D3;
-- Node name is '|DELED:1|:262' from file "deled.tdf" line 25, column 26
-- Equation name is '_LC8_B7', type is buried
_LC8_B7 = LCELL( _EQ010);
_EQ010 = D2 & D3
# !D0 & D3
# !D0 & !D2
# !D0 & D1
# D1 & D3;
-- Node name is '|DELED:1|~264~1' from file "deled.tdf" line 25, column 28
-- Equation name is '_LC1_B2', type is buried
-- synthesized logic cell
_LC1_B2 = LCELL( _EQ011);
_EQ011 = !D0 & D1 & D2;
-- Node name is '|DELED:1|:264' from file "deled.tdf" line 25, column 28
-- Equation name is '_LC3_B6', type is buried
_LC3_B6 = LCELL( _EQ012);
_EQ012 = !D0 & D2
# !D0 & D3
# !D0 & !D1
# D1 & D3
# !D1 & D2 & !D3
# !D2 & D3;
-- Node name is '|DELED:1|~266~1' from file "deled.tdf" line 25, column 30
-- Equation name is '_LC7_B2', type is buried
-- synthesized logic cell
_LC7_B2 = LCELL( _EQ013);
_EQ013 = !D0 & !D2 & D3
# !D1 & !D2 & D3
# !D0 & !D1 & D2 & !D3
# D0 & D1 & !D2 & !D3
# D0 & !D1 & D3;
-- Node name is '|DELED:1|~266~2' from file "deled.tdf" line 25, column 30
-- Equation name is '_LC6_B2', type is buried
-- synthesized logic cell
_LC6_B2 = LCELL( _EQ014);
_EQ014 = D0 & !D1 & D2 & !D3
# D0 & D1 & D3;
-- Node name is '|DELED:1|:266' from file "deled.tdf" line 25, column 30
-- Equation name is '_LC5_B2', type is buried
_LC5_B2 = LCELL( _EQ015);
_EQ015 = _LC1_B2
# _LC6_B2
# _LC7_B2
# !_LC3_B2;
-- Node name is '|74161:10|f74161:sub|:9' = '|74161:10|f74161:sub|QA'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = DFFE(!_LC3_A1, GLOBAL( CLK), GLOBAL( RESET), VCC, VCC);
-- Node name is '|74161:10|f74161:sub|:87' = '|74161:10|f74161:sub|QB'
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = DFFE( _EQ016, GLOBAL( CLK), GLOBAL( RESET), VCC, VCC);
_EQ016 = !_LC3_A1 & _LC5_A1
# _LC3_A1 & !_LC5_A1;
-- Node name is '|74161:10|f74161:sub|:99' = '|74161:10|f74161:sub|QC'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = DFFE( _EQ017, GLOBAL( CLK), GLOBAL( RESET), VCC, VCC);
_EQ017 = _LC1_A1 & !_LC5_A1
# _LC1_A1 & !_LC3_A1
# !_LC1_A1 & _LC3_A1 & _LC5_A1;
Project Information c:\edatest\altera\test4\1\t4_1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 8,861K
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