📄 t4_2.rpt
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Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\edatest\altera\test4\2\t4_2.rpt
t4_2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 CLK
Device-Specific Information: c:\edatest\altera\test4\2\t4_2.rpt
t4_2
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 RESET
Device-Specific Information: c:\edatest\altera\test4\2\t4_2.rpt
t4_2
** EQUATIONS **
CLK : INPUT;
RESET : INPUT;
-- Node name is 'A'
-- Equation name is 'A', type is output
A = _LC3_A2;
-- Node name is 'B'
-- Equation name is 'B', type is output
B = _LC1_A3;
-- Node name is 'C'
-- Equation name is 'C', type is output
C = _LC8_A5;
-- Node name is 'D'
-- Equation name is 'D', type is output
D = _LC5_A6;
-- Node name is 'E'
-- Equation name is 'E', type is output
E = _LC2_A4;
-- Node name is 'F'
-- Equation name is 'F', type is output
F = _LC1_A1;
-- Node name is 'G'
-- Equation name is 'G', type is output
G = _LC7_A1;
-- Node name is 'SEL0'
-- Equation name is 'SEL0', type is output
SEL0 = _LC3_A1;
-- Node name is 'SEL1'
-- Equation name is 'SEL1', type is output
SEL1 = _LC1_A8;
-- Node name is 'SEL2'
-- Equation name is 'SEL2', type is output
SEL2 = _LC5_A7;
-- Node name is '|DELED:8|:132' from file "deled.tdf" line 17, column 5
-- Equation name is '_LC2_A2', type is buried
!_LC2_A2 = _LC2_A2~NOT;
_LC2_A2~NOT = LCELL( _EQ001);
_EQ001 = _LC1_A8 & !_LC1_A9 & _LC3_A1 & _LC5_A7;
-- Node name is '|DELED:8|:227' from file "deled.tdf" line 23, column 20
-- Equation name is '_LC1_A3', type is buried
_LC1_A3 = LCELL( _EQ002);
_EQ002 = !_LC1_A8 & !_LC1_A9 & !_LC3_A1
# _LC1_A8 & !_LC1_A9 & _LC3_A1
# !_LC1_A8 & _LC1_A9 & _LC3_A1
# !_LC1_A9 & !_LC5_A7
# !_LC3_A1 & !_LC5_A7
# !_LC1_A8 & !_LC5_A7;
-- Node name is '|DELED:8|:229' from file "deled.tdf" line 23, column 22
-- Equation name is '_LC8_A5', type is buried
_LC8_A5 = LCELL( _EQ003);
_EQ003 = !_LC1_A9 & _LC5_A7
# !_LC1_A8 & _LC3_A1 & _LC5_A7
# _LC1_A8 & _LC3_A1 & !_LC5_A7
# _LC1_A9 & !_LC5_A7
# !_LC1_A8 & !_LC1_A9;
-- Node name is '|DELED:8|~245~1' from file "deled.tdf" line 24, column 24
-- Equation name is '_LC5_A2', type is buried
-- synthesized logic cell
_LC5_A2 = LCELL( _EQ004);
_EQ004 = !_LC1_A8 & !_LC1_A9 & _LC3_A1 & _LC5_A7
# _LC1_A8 & !_LC1_A9 & !_LC3_A1 & !_LC5_A7;
-- Node name is '|DELED:8|:245' from file "deled.tdf" line 24, column 24
-- Equation name is '_LC5_A6', type is buried
_LC5_A6 = LCELL( _EQ005);
_EQ005 = _LC1_A8 & !_LC1_A9 & !_LC3_A1
# _LC1_A8 & !_LC3_A1 & _LC5_A7
# !_LC1_A8 & _LC3_A1 & _LC5_A7
# !_LC1_A8 & _LC1_A9 & !_LC5_A7
# _LC1_A9 & _LC3_A1 & !_LC5_A7
# _LC1_A8 & !_LC1_A9 & !_LC5_A7
# _LC1_A9 & !_LC3_A1 & _LC5_A7
# !_LC1_A9 & !_LC3_A1 & !_LC5_A7;
-- Node name is '|DELED:8|~260~1' from file "deled.tdf" line 25, column 18
-- Equation name is '_LC1_A2', type is buried
-- synthesized logic cell
_LC1_A2 = LCELL( _EQ006);
_EQ006 = _LC1_A9 & !_LC3_A1 & _LC5_A7
# _LC1_A8 & _LC1_A9 & _LC5_A7
# _LC1_A8 & !_LC3_A1 & _LC5_A7
# !_LC1_A8 & !_LC1_A9 & !_LC3_A1 & !_LC5_A7
# _LC1_A8 & _LC1_A9 & !_LC3_A1;
-- Node name is '|DELED:8|:260' from file "deled.tdf" line 25, column 18
-- Equation name is '_LC3_A2', type is buried
_LC3_A2 = LCELL( _EQ007);
_EQ007 = !_LC2_A2
# _LC4_A2
# _LC1_A2
# _LC5_A2;
-- Node name is '|DELED:8|:262' from file "deled.tdf" line 25, column 26
-- Equation name is '_LC2_A4', type is buried
_LC2_A4 = LCELL( _EQ008);
_EQ008 = !_LC3_A1 & !_LC5_A7
# _LC1_A8 & _LC1_A9
# _LC1_A9 & !_LC3_A1
# _LC1_A9 & _LC5_A7
# _LC1_A8 & !_LC3_A1;
-- Node name is '|DELED:8|:264' from file "deled.tdf" line 25, column 28
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = LCELL( _EQ009);
_EQ009 = !_LC1_A8 & !_LC3_A1
# _LC1_A8 & _LC1_A9
# _LC1_A9 & !_LC3_A1
# _LC1_A9 & !_LC5_A7
# !_LC1_A8 & !_LC1_A9 & _LC5_A7
# !_LC3_A1 & _LC5_A7;
-- Node name is '|DELED:8|~266~1' from file "deled.tdf" line 25, column 30
-- Equation name is '_LC4_A2', type is buried
-- synthesized logic cell
_LC4_A2 = LCELL( _EQ010);
_EQ010 = !_LC1_A8 & _LC1_A9 & !_LC5_A7
# _LC1_A8 & !_LC1_A9 & _LC3_A1 & !_LC5_A7;
-- Node name is '|DELED:8|:266' from file "deled.tdf" line 25, column 30
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = LCELL( _EQ011);
_EQ011 = !_LC1_A8 & !_LC1_A9 & _LC5_A7
# !_LC1_A9 & !_LC3_A1 & _LC5_A7
# _LC1_A8 & _LC1_A9
# _LC1_A9 & !_LC5_A7
# _LC1_A9 & _LC3_A1
# _LC1_A8 & !_LC5_A7;
-- Node name is '|74161:3|f74161:sub|:9' = '|74161:3|f74161:sub|QA'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = DFFE(!_LC3_A1, GLOBAL( CLK), GLOBAL( RESET), VCC, VCC);
-- Node name is '|74161:3|f74161:sub|:87' = '|74161:3|f74161:sub|QB'
-- Equation name is '_LC1_A8', type is buried
_LC1_A8 = DFFE( _EQ012, GLOBAL( CLK), GLOBAL( RESET), VCC, VCC);
_EQ012 = !_LC1_A8 & _LC3_A1
# _LC1_A8 & !_LC3_A1;
-- Node name is '|74161:3|f74161:sub|:99' = '|74161:3|f74161:sub|QC'
-- Equation name is '_LC5_A7', type is buried
_LC5_A7 = DFFE( _EQ013, GLOBAL( CLK), GLOBAL( RESET), VCC, VCC);
_EQ013 = !_LC3_A1 & _LC5_A7
# !_LC1_A8 & _LC5_A7
# _LC1_A8 & _LC3_A1 & !_LC5_A7;
-- Node name is '|74161:3|f74161:sub|:110' = '|74161:3|f74161:sub|QD'
-- Equation name is '_LC1_A9', type is buried
_LC1_A9 = DFFE( _EQ014, GLOBAL( CLK), GLOBAL( RESET), VCC, VCC);
_EQ014 = _LC1_A9 & !_LC5_A7
# _LC1_A9 & !_LC3_A1
# !_LC1_A8 & _LC1_A9
# _LC1_A8 & !_LC1_A9 & _LC3_A1 & _LC5_A7;
Project Information c:\edatest\altera\test4\2\t4_2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:02
Partitioner 00:00:01
Fitter 00:00:03
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:08
Memory Allocated
-----------------
Peak memory allocated during compilation = 8,813K
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