📄 csl_emif.h
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/** EMIF Minor Revision */
Uint16 minorRev;
} CSL_EmifRevStatus;
/** @brief EMIF DDR Status structure
*
* This structure holds the DDR PHY Ready, Train CS1 & CS0 and DDR status
* fields.
*/
typedef struct {
/** DDR PHY ready */
Uint16 phyDllRdy;
/** Train CS1 */
Uint16 trainCS1;
/** Train CS0 */
Uint16 trainCS0;
/** Double Rate */
Uint16 ddr;
} CSL_EmifDdrStatus;
/** @brief EMIF DDR PHY Status structure
*
* This structure holds the fields in the DDR PHY Status Register.
*/
typedef struct {
/** TLDQ3SEL field */
Uint16 tldq3sel;
/** TAPLVL1DQ3 field */
Uint16 taplvl1dq3;
/** TLDQ2SEL field */
Uint16 tldq2sel;
/** TAPLVL1DQ2 field */
Uint16 taplvl1dq2;
/** TLDQ1SEL field */
Uint16 tldq1sel;
/** TAPLVL1DQ1 field */
Uint16 taplvl1dq1;
/** TLDQ0SEL field */
Uint16 tldq0sel;
/** TAPLVL1DQ0 field */
Uint16 taplvl1dq0;
} CSL_EmifDdrPhyStatus;
/** @brief NAND FLASH ECC structure
*
* This structure holds the fields in the Nand Flash ECC Register.
*/
typedef struct {
/** ECC code calculated while reading/writing NAND Flash.
* For 8_bit NAND Flash, p1o, p2o, and p4o are column parities. p8o to
* p2048o are row parities.For 16_bit NAND Flash, p1o, p2o, p4o and p8o
* are column parities. p16o to p2048o are row parities.
* Odd Polarity for p2048
*/
Uint16 p2048o;
/** Odd Polarity for p1024 */
Uint16 p1024o;
/** Odd Polarity for p512 */
Uint16 p512o;
/** Odd Polarity for p256 */
Uint16 p256o;
/** Odd Polarity for p128 */
Uint16 p128o;
/** Odd Polarity for p64 */
Uint16 p64o;
/** Odd Polarity for p32 */
Uint16 p32o;
/** Odd Polarity for p16 */
Uint16 p16o;
/** Odd Polarity for p8 */
Uint16 p8o;
/** Odd Polarity for p4 */
Uint16 p4o;
/** Odd Polarity for p2 */
Uint16 p2o;
/** Odd Polarity for p1 */
Uint16 p1o;
/** Even Polarity for p2048 */
Uint16 p2048e;
/** Even Polarity for p1028 */
Uint16 p1024e;
/** Even Polarity for p512 */
Uint16 p512e;
/** Even Polarity for p256 */
Uint16 p256e;
/** Even Polarity for p128 */
Uint16 p128e;
/** Even Polarity for p64 */
Uint16 p64e;
/** Even Polarity for p32 */
Uint16 p32e;
/** Even Polarity for p16 */
Uint16 p16e;
/** Even Polarity for p8 */
Uint16 p8e;
/** Even Polarity for p4 */
Uint16 p4e;
/** Even Polarity for p2 */
Uint16 p2e;
/** Even Polarity for p1 */
Uint16 p1e;
} CSL_EmifNandFlashECC;
/** @brief Enumeration for queries passed to @a CSL_emifGetHwStatus()
*
* This is used to get the status of different operations or to get the
* existing setup of EMIF.
*/
typedef enum {
/** Get the EMIF module ID and revision numbers (response type:
* @a (CSL_EmifRevStatus*))
*/
CSL_EMIF_QUERY_REV_ID_STATUS = 1,
/** Get the EMIF endianness (response type: @a Uint16 *) */
CSL_EMIF_QUERY_ENDIANNESS = 2,
/** Get the EMIF rate information(response type: @a Uint16 *) */
CSL_EMIF_QUERY_RATE = 3,
/** Get the EMIF DDR status information(response type:
* @a (CSL_EmifDdrStatus *))
*/
CSL_EMIF_QUERY_DDR_STATUS = 4,
/** Get the EMIF DDR PHY status information(response type:
* @a (CSL_EmifDdrPhyStatus *))
*/
CSL_EMIF_QUERY_DDR_PHY_STATUS = 5,
/** Get the total SDRAM accesses (response type: @a Uint16 *) */
CSL_EMIF_QUERY_SDRAM_ACCESS = 6,
/** Get the total SDRAM accesses that needed an activate command
* (response type: @a Uint16 *)
*/
CSL_EMIF_QUERY_SDRAM_ACTIVATE = 7,
/** Get the DDR PHY ID and Revision information
* (response type: @a Uint32 *)
*/
CSL_EMIF_QUERY_DDR_ID_REV = 8,
/** Get the Line Trap Interrupt Status (response type: @a Uint16 *) */
CSL_EMIF_QUERY_LT_INT_STATUS = 9,
/** Get the Asynchronous Timeout Interrupt Status
* (response type: @a Uint16 *)
*/
CSL_EMIF_QUERY_AT_INT_STATUS = 10,
/** Get the IO status (response type: @a Uint16 *) */
CSL_EMIF_QUERY_IO_STATUS = 11,
/** Get the NAND Flash Status (response type: @a Uint16 *) */
CSL_EMIF_QUERY_NAND_FLASH_STATUS = 12,
/** Read the NAND FLASH ECC for Chip select 5 (response type:
* @a (CSL_EmifNandFlashECC *))
*/
CSL_EMIF_QUERY_CS5_NAND_FLASH_ECC = 13,
/** Read the NAND FLASH ECC for Chip select 4 (response type:
* @a (CSL_EmifNandFlashECC *))
*/
CSL_EMIF_QUERY_CS4_NAND_FLASH_ECC = 14,
/** Read the NAND FLASH ECC for Chip select 3 (response type:
* @a (CSL_EmifNandFlashECC *))
*/
CSL_EMIF_QUERY_CS3_NAND_FLASH_ECC = 15,
/** Read the NAND FLASH ECC for Chip select 2 (response type:
* @a (CSL_EmifNandFlashECC *))
*/
CSL_EMIF_QUERY_CS2_NAND_FLASH_ECC = 16
} CSL_EmifHwStatusQuery;
/** @brief Enumeration for queries passed to @a CSL_emifHwControl()
*
* This is used to select the commands to control the operations
* existing setup of EMIF. The arguments to be passed with each
* enumeration if any are specified next to the enumeration.
*/
typedef enum {
/** Set the DDR Refresh Threshold : argument @a (Uint16 *) */
CSL_EMIF_CMD_SET_DDR_REF_THRESH = 1,
/** Set the Refresh Rate : argument @a (Uint16 *) */
CSL_EMIF_CMD_REF_RATE = 2,
/** Set the DDR PHY Control TAP value: argument @a (Uint16 *) */
CSL_EMIF_CMD_SET_DDR_TAPV = 3,
/** Set the RTM PHY training time: argument @a (Uint16 *) */
CSL_EMIF_CMD_DDR_TRAIN = 4,
/** Enable the Line Trap Interrupt : no argument */
CSL_EMIF_CMD_LT_ENABLE = 5,
/** Disable the Line Trap Interrupt : no argument */
CSL_EMIF_CMD_LT_DISABLE = 6,
/** Enable the Asynchronous Timeout Interrupt : no argument */
CSL_EMIF_CMD_AT_ENABLE = 7,
/** Disable the Asynchronous Timeout Interrupt : no argument */
CSL_EMIF_CMD_AT_DISABLE = 8,
/** Control word for IO Control : argument @a (Uint16*) */
CSL_EMIF_CMD_IO_CONTROL = 9,
/** Start ECC calculation for Chip Select 5 : no argument*/
CSL_EMIF_CMD_CS5_ECC_START = 10,
/** Start ECC calculation for Chip Select 4 : no argument */
CSL_EMIF_CMD_CS4_ECC_START = 11,
/** Start ECC calculation for Chip Select 3 : no argument */
CSL_EMIF_CMD_CS3_ECC_START = 12,
/** Start ECC calculation for Chip Select 2 : no argument */
CSL_EMIF_CMD_CS2_ECC_START = 13,
/** Enable the CS5 NAND FLASH : no argument */
CSL_EMIF_CMD_CS5_NAND_ENABLE = 14,
/** Disable the CS5 NAND FLASH : no argument */
CSL_EMIF_CMD_CS5_NAND_DISABLE = 15,
/** Enable the CS4 NAND FLASH : no argument */
CSL_EMIF_CMD_CS4_NAND_ENABLE = 16,
/** Disable the CS4 NAND FLASH : no argument */
CSL_EMIF_CMD_CS4_NAND_DISABLE = 17,
/** Enable the CS3 NAND FLASH : no argument */
CSL_EMIF_CMD_CS3_NAND_ENABLE = 18,
/** Disable the CS3 NAND FLASH : no argument */
CSL_EMIF_CMD_CS3_NAND_DISABLE = 19,
/** Enable the CS2 NAND FLASH : no argument */
CSL_EMIF_CMD_CS2_NAND_ENABLE = 20,
/** Disable the CS2 NAND FLASH : no argument */
CSL_EMIF_CMD_CS2_NAND_DISABLE = 21
} CSL_EmifHwControlCmd;
/* Setup defaults for sdram timing config, all sdram configs are disabled,
* config for async bank config1, config for async bank config2, config for
* async bank config3, config for async bank config4, DDR physical control
* defaults, disable al nand flash control
*/
/** @brief The defaults of hardware setup structure */
#define CSL_EMIF_HWSETUP_DEFAULTS { \
{ CSL_EMIF_WAIT_POLARITY_HI, CSL_EMIF_WAIT_POLARITY_HI, \
CSL_EMIF_WAIT_POLARITY_HI, CSL_EMIF_WAIT_POLARITY_HI, \
CSL_EMIF_CHIP_SEL_LOW, CSL_EMIF_CHIP_SEL_LOW, \
CSL_EMIF_CHIP_SEL_LOW, CSL_EMIF_CHIP_SEL_LOW, \
CSL_EMIF_MAX_WAIT }, \
{ CSL_EMIF_REFRESH_TRESH, CSL_EMIF_REF_RATE }, \
{ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }, \
{ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }, \
{ NULL, NULL, NULL, CSL_EMIF_WRITE_SETUP, CSL_EMIF_WRITE_HOLD, \
CSL_EMIF_READ_SETUP, CSL_EMIF_READ_HOLD, CSL_EMIF_ASYN_SIZE }, \
{ NULL, NULL, NULL, CSL_EMIF_WRITE_SETUP, CSL_EMIF_WRITE_HOLD, \
CSL_EMIF_READ_SETUP, CSL_EMIF_READ_HOLD, CSL_EMIF_ASYN_SIZE }, \
{ NULL, NULL, NULL, CSL_EMIF_WRITE_SETUP, CSL_EMIF_WRITE_HOLD, \
CSL_EMIF_READ_SETUP, CSL_EMIF_READ_HOLD, CSL_EMIF_ASYN_SIZE }, \
{ NULL, NULL, NULL, CSL_EMIF_WRITE_SETUP, CSL_EMIF_WRITE_HOLD, \
CSL_EMIF_READ_SETUP, CSL_EMIF_READ_HOLD, CSL_EMIF_ASYN_SIZE }, \
{ NULL, CSL_EMIF_WRITE_HOLD, CSL_EMIF_TRAIN }, \
{ NULL, NULL, NULL, NULL } \
};
/** @brief The default config structure */
#define CSL_EMIF_CONFIG_DEFAULTS { \
CSL_EMIF_AWCCR_RESETVAL, \
CSL_EMIF_SDBCR_RESETVAL, \
CSL_EMIF_SDRCR_RESETVAL, \
CSL_EMIF_AB1CR_RESETVAL, \
CSL_EMIF_AB2CR_RESETVAL, \
CSL_EMIF_AB3CR_RESETVAL, \
CSL_EMIF_AB4CR_RESETVAL, \
CSL_EMIF_SDTIMR_RESETVAL, \
CSL_EMIF_DDRPHYCR_RESETVAL, \
CSL_EMIF_SDSRETR_RESETVAL, \
CSL_EMIF_EIRR_RESETVAL, \
CSL_EMIF_EIMR_RESETVAL, \
CSL_EMIF_EIMSR_RESETVAL, \
CSL_EMIF_EIMCR_RESETVAL, \
CSL_EMIF_IOCTRLR_RESETVAL, \
CSL_EMIF_NANDFCR_RESETVAL \
};
/** @brief External memory interface config structure which is used in
* CSL_emifHwSetupRaw function
*/
typedef struct {
/** External memory interface async wait cycle config register */
volatile Uint32 AWCCR;
/** External memory interface SDRAM banck config register */
volatile Uint32 SDBCR;
/** External memory interface SDRAM refresh control register */
volatile Uint32 SDRCR;
/** External memory interface async banck config register 1 */
volatile Uint32 AB1CR;
/** External memory interface async banck config register 2 */
volatile Uint32 AB2CR;
/** External memory interface async banck config register 3 */
volatile Uint32 AB3CR;
/** External memory interface async banck config register 4 */
volatile Uint32 AB4CR;
/** External memory interface SDRAM timing register */
volatile Uint32 SDTIMR;
/** External memory interface DDR PHY config register */
volatile Uint32 DDRPHYCR;
/** External memory interface SDRAM Self Refresh Exit Timing Register */
volatile Uint32 SDSRETR;
/** External memory interface interrupt raw register */
volatile Uint32 EIRR;
/** External memory interface interrupt masked register */
volatile Uint32 EIMR;
/** External memory interface interrupt mask set register */
volatile Uint32 EIMSR;
/** External memory interface interrupt mask clear register */
volatile Uint32 EIMCR;
/** External memory interface io control register */
volatile Uint32 IOCTRLR;
/** External memory interface NAND flash control register */
volatile Uint32 NANDFCR;
} CSL_EmifConfig;
/**
* @brief Module specific context information. Present implementation of external
* memory interface timer CSL doesn't have any context information.
*/
typedef struct {
/** Context information of external memory interface CSL.
* The below declaration is just a place-holder for future implementation.
*/
Uint16 contextInfo;
} CSL_EmifContext;
/**
* @brief Module specific parameters. Present implementation of external memory
* interface CSL doesn't have any module specific parameters.
*/
typedef struct {
/** Bit mask to be used for module specific parameters. The below
* declaration is just a place-holder for future implementation.
*/
CSL_BitMask16 flags;
} CSL_EmifParam;
/**
* @brief This structure contains the base-address information for the peripheral
* instance
*/
typedef struct {
/** Base-address of the configuration registers of the peripheral */
CSL_EmifRegsOvly regs;
} CSL_EmifBaseAddress;
/**************************************************************************\
* EMIF global function declarations
\**************************************************************************/
/** ===========================================================================
* @n@b CSL_emifInit
*
* @b Description
* @n This function is idempotent in that calling it many times is same as
* calling it once. This function initializes the EMIF CSL data structures.
*
* <b> Usage Constraints: </b>
* CSL system initialization must be successfully completed by invoking
* @a CSL_sysInit() before calling this function. This function should be
* called before using any of the CSL APIs
*
* @b Arguments
@verbatim
pContext Context information for the instance. Should be NULL
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Always returns
*
* <b> Pre Condition </b>
* @n None
*
* <b> Post Condition </b>
* @n None
*
* @b Modifies
* @n None
*
* @b Example
* @verbatim
...
CSL_sysInit( NULL );
if (CSL_SOK != CSL_emifInit( NULL )) {
return;
}
@endverbatim
*
* @return returns the status of the operation
*
* ============================================================================
*/
CSL_Status CSL_emifInit (
CSL_EmifContext * pContext
);
/** =============================================================================
* @n@b CSL_emifOpen
*
* @b Description
* @n This function returns the handle to the EMIF instance. This
* handle is passed to all other CSL APIs.
*
* @b Arguments
* @verbatim
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