cslr_sys.h

ccs下对dm6446的测试程序

#define CSL_SYS_DSPBOOTADDR_RESETVAL     (0x42200000u)

/* SUSPSRC */

#define CSL_SYS_SUSPSRC_TIMR2SRC_MASK    (0x20000000u)
#define CSL_SYS_SUSPSRC_TIMR2SRC_SHIFT   (0x0000001Du)
#define CSL_SYS_SUSPSRC_TIMR2SRC_RESETVAL (0x00000000u)

/*----TIMR2SRC Tokens----*/
#define CSL_SYS_SUSPSRC_TIMR2SRC_ARMEMU  (0x00000000u)
#define CSL_SYS_SUSPSRC_TIMR2SRC_GEMEMU  (0x00000001u)

#define CSL_SYS_SUSPSRC_TIMR1SRC_MASK    (0x10000000u)
#define CSL_SYS_SUSPSRC_TIMR1SRC_SHIFT   (0x0000001Cu)
#define CSL_SYS_SUSPSRC_TIMR1SRC_RESETVAL (0x00000000u)

/*----TIMR1SRC Tokens----*/
#define CSL_SYS_SUSPSRC_TIMR1SRC_ARMEMU  (0x00000000u)
#define CSL_SYS_SUSPSRC_TIMR1SRC_GEMEMU  (0x00000001u)

#define CSL_SYS_SUSPSRC_TIMR0SRC_MASK    (0x08000000u)
#define CSL_SYS_SUSPSRC_TIMR0SRC_SHIFT   (0x0000001Bu)
#define CSL_SYS_SUSPSRC_TIMR0SRC_RESETVAL (0x00000000u)

/*----TIMR0SRC Tokens----*/
#define CSL_SYS_SUSPSRC_TIMR0SRC_ARMEMU  (0x00000000u)
#define CSL_SYS_SUSPSRC_TIMR0SRC_GEMEMU  (0x00000001u)

#define CSL_SYS_SUSPSRC_GPIOSRC_MASK     (0x04000000u)
#define CSL_SYS_SUSPSRC_GPIOSRC_SHIFT    (0x0000001Au)
#define CSL_SYS_SUSPSRC_GPIOSRC_RESETVAL (0x00000000u)

/*----GPIOSRC Tokens----*/
#define CSL_SYS_SUSPSRC_GPIOSRC_ARMEMU   (0x00000000u)
#define CSL_SYS_SUSPSRC_GPIOSRC_GEMEMU   (0x00000001u)

#define CSL_SYS_SUSPSRC_PWM2SRC_MASK     (0x02000000u)
#define CSL_SYS_SUSPSRC_PWM2SRC_SHIFT    (0x00000019u)
#define CSL_SYS_SUSPSRC_PWM2SRC_RESETVAL (0x00000000u)

/*----PWM2SRC Tokens----*/
#define CSL_SYS_SUSPSRC_PWM2SRC_ARMEMU   (0x00000000u)
#define CSL_SYS_SUSPSRC_PWM2SRC_GEMEMU   (0x00000001u)

#define CSL_SYS_SUSPSRC_PWM1SRC_MASK     (0x01000000u)
#define CSL_SYS_SUSPSRC_PWM1SRC_SHIFT    (0x00000018u)
#define CSL_SYS_SUSPSRC_PWM1SRC_RESETVAL (0x00000000u)

/*----PWM1SRC Tokens----*/
#define CSL_SYS_SUSPSRC_PWM1SRC_ARMEMU   (0x00000000u)
#define CSL_SYS_SUSPSRC_PWM1SRC_GEMEMU   (0x00000001u)

#define CSL_SYS_SUSPSRC_PWM0SRC_MASK     (0x00800000u)
#define CSL_SYS_SUSPSRC_PWM0SRC_SHIFT    (0x00000017u)
#define CSL_SYS_SUSPSRC_PWM0SRC_RESETVAL (0x00000000u)

/*----PWM0SRC Tokens----*/
#define CSL_SYS_SUSPSRC_PWM0SRC_ARMEMU   (0x00000000u)
#define CSL_SYS_SUSPSRC_PWM0SRC_GEMEMU   (0x00000001u)

#define CSL_SYS_SUSPSRC_SPISRC_MASK      (0x00400000u)
#define CSL_SYS_SUSPSRC_SPISRC_SHIFT     (0x00000016u)
#define CSL_SYS_SUSPSRC_SPISRC_RESETVAL  (0x00000000u)

/*----SPISRC Tokens----*/
#define CSL_SYS_SUSPSRC_SPISRC_ARMEMU    (0x00000000u)
#define CSL_SYS_SUSPSRC_SPISRC_GEMEMU    (0x00000001u)

#define CSL_SYS_SUSPSRC_UART2SRC_MASK    (0x00200000u)
#define CSL_SYS_SUSPSRC_UART2SRC_SHIFT   (0x00000015u)
#define CSL_SYS_SUSPSRC_UART2SRC_RESETVAL (0x00000000u)

/*----UART2SRC Tokens----*/
#define CSL_SYS_SUSPSRC_UART2SRC_ARMEMU  (0x00000000u)
#define CSL_SYS_SUSPSRC_UART2SRC_GEMEMU  (0x00000001u)

#define CSL_SYS_SUSPSRC_UART1SRC_MASK    (0x00100000u)
#define CSL_SYS_SUSPSRC_UART1SRC_SHIFT   (0x00000014u)
#define CSL_SYS_SUSPSRC_UART1SRC_RESETVAL (0x00000000u)

/*----UART1SRC Tokens----*/
#define CSL_SYS_SUSPSRC_UART1SRC_ARMEMU  (0x00000000u)
#define CSL_SYS_SUSPSRC_UART1SRC_GEMEMU  (0x00000001u)

#define CSL_SYS_SUSPSRC_UART0SRC_MASK    (0x00080000u)
#define CSL_SYS_SUSPSRC_UART0SRC_SHIFT   (0x00000013u)
#define CSL_SYS_SUSPSRC_UART0SRC_RESETVAL (0x00000000u)

/*----UART0SRC Tokens----*/
#define CSL_SYS_SUSPSRC_UART0SRC_ARMEMU  (0x00000000u)
#define CSL_SYS_SUSPSRC_UART0SRC_GEMEMU  (0x00000001u)

#define CSL_SYS_SUSPSRC_I2CSRC_MASK      (0x00040000u)
#define CSL_SYS_SUSPSRC_I2CSRC_SHIFT     (0x00000012u)
#define CSL_SYS_SUSPSRC_I2CSRC_RESETVAL  (0x00000000u)

/*----I2CSRC Tokens----*/
#define CSL_SYS_SUSPSRC_I2CSRC_ARMEMU    (0x00000000u)
#define CSL_SYS_SUSPSRC_I2CSRC_GEMEMU    (0x00000001u)

#define CSL_SYS_SUSPSRC_MCBSPSRC_MASK    (0x00020000u)
#define CSL_SYS_SUSPSRC_MCBSPSRC_SHIFT   (0x00000011u)
#define CSL_SYS_SUSPSRC_MCBSPSRC_RESETVAL (0x00000000u)

/*----McBSPSRC Tokens----*/
#define CSL_SYS_SUSPSRC_MCBSPSRC_ARMEMU  (0x00000000u)
#define CSL_SYS_SUSPSRC_MCBSPSRC_GEMEMU  (0x00000001u)

#define CSL_SYS_SUSPSRC_UHPISRC_MASK     (0x00001000u)
#define CSL_SYS_SUSPSRC_UHPISRC_SHIFT    (0x0000000Cu)
#define CSL_SYS_SUSPSRC_UHPISRC_RESETVAL (0x00000000u)

/*----UHPISRC Tokens----*/
#define CSL_SYS_SUSPSRC_UHPISRC_ARMEMU   (0x00000000u)
#define CSL_SYS_SUSPSRC_UHPISRC_GEMEMU   (0x00000001u)

#define CSL_SYS_SUSPSRC_USBSRC_MASK      (0x00000200u)
#define CSL_SYS_SUSPSRC_USBSRC_SHIFT     (0x00000009u)
#define CSL_SYS_SUSPSRC_USBSRC_RESETVAL  (0x00000000u)

/*----USBSRC Tokens----*/
#define CSL_SYS_SUSPSRC_USBSRC_ARMEMU    (0x00000000u)
#define CSL_SYS_SUSPSRC_USBSRC_GEMEMU    (0x00000001u)

#define CSL_SYS_SUSPSRC_RESETVAL         (0x00000000u)

/* INTGEN */

#define CSL_SYS_INTGEN_INT_ARM1_STAT_MASK (0x20000000u)
#define CSL_SYS_INTGEN_INT_ARM1_STAT_SHIFT (0x0000001Du)
#define CSL_SYS_INTGEN_INT_ARM1_STAT_RESETVAL (0x00000000u)

/*----INT_ARM1_STAT Tokens----*/
#define CSL_SYS_INTGEN_INT_ARM1_STAT_NOINT (0x00000000u)
#define CSL_SYS_INTGEN_INT_ARM1_STAT_ACTIVEINT (0x00000001u)

#define CSL_SYS_INTGEN_INT_ARM0_STAT_MASK (0x10000000u)
#define CSL_SYS_INTGEN_INT_ARM0_STAT_SHIFT (0x0000001Cu)
#define CSL_SYS_INTGEN_INT_ARM0_STAT_RESETVAL (0x00000000u)

/*----INT_ARM0_STAT Tokens----*/
#define CSL_SYS_INTGEN_INT_ARM0_STAT_NOINT (0x00000000u)
#define CSL_SYS_INTGEN_INT_ARM0_STAT_ACTIVEINT (0x00000001u)

#define CSL_SYS_INTGEN_INT_DSP3_STAT_MASK (0x00800000u)
#define CSL_SYS_INTGEN_INT_DSP3_STAT_SHIFT (0x00000017u)
#define CSL_SYS_INTGEN_INT_DSP3_STAT_RESETVAL (0x00000000u)

/*----INT_DSP3_STAT Tokens----*/
#define CSL_SYS_INTGEN_INT_DSP3_STAT_NOINT (0x00000000u)
#define CSL_SYS_INTGEN_INT_DSP3_STAT_ACTIVEINT (0x00000001u)

#define CSL_SYS_INTGEN_INT_DSP2_STAT_MASK (0x00400000u)
#define CSL_SYS_INTGEN_INT_DSP2_STAT_SHIFT (0x00000016u)
#define CSL_SYS_INTGEN_INT_DSP2_STAT_RESETVAL (0x00000000u)

/*----INT_DSP2_STAT Tokens----*/
#define CSL_SYS_INTGEN_INT_DSP2_STAT_NOINT (0x00000000u)
#define CSL_SYS_INTGEN_INT_DSP2_STAT_ACTIVEINT (0x00000001u)

#define CSL_SYS_INTGEN_INT_DSP1_STAT_MASK (0x00200000u)
#define CSL_SYS_INTGEN_INT_DSP1_STAT_SHIFT (0x00000015u)
#define CSL_SYS_INTGEN_INT_DSP1_STAT_RESETVAL (0x00000000u)

/*----INT_DSP1_STAT Tokens----*/
#define CSL_SYS_INTGEN_INT_DSP1_STAT_NOINT (0x00000000u)
#define CSL_SYS_INTGEN_INT_DSP1_STAT_ACTIVEINT (0x00000001u)

#define CSL_SYS_INTGEN_INT_DSP0_STAT_MASK (0x00100000u)
#define CSL_SYS_INTGEN_INT_DSP0_STAT_SHIFT (0x00000014u)
#define CSL_SYS_INTGEN_INT_DSP0_STAT_RESETVAL (0x00000000u)

/*----INT_DSP0_STAT Tokens----*/
#define CSL_SYS_INTGEN_INT_DSP0_STAT_NOINT (0x00000000u)
#define CSL_SYS_INTGEN_INT_DSP0_STAT_ACTIVEINT (0x00000001u)

#define CSL_SYS_INTGEN_INT_NMI_STAT_MASK (0x00010000u)
#define CSL_SYS_INTGEN_INT_NMI_STAT_SHIFT (0x00000010u)
#define CSL_SYS_INTGEN_INT_NMI_STAT_RESETVAL (0x00000000u)

/*----INT_NMI_STAT Tokens----*/
#define CSL_SYS_INTGEN_INT_NMI_STAT_NOINT (0x00000000u)
#define CSL_SYS_INTGEN_INT_NMI_STAT_ACTIVEINT (0x00000001u)

#define CSL_SYS_INTGEN_INT_ARM1_MASK     (0x00002000u)
#define CSL_SYS_INTGEN_INT_ARM1_SHIFT    (0x0000000Du)
#define CSL_SYS_INTGEN_INT_ARM1_RESETVAL (0x00000000u)

/*----INT_ARM1 Tokens----*/
#define CSL_SYS_INTGEN_INT_ARM1_NOINT    (0x00000000u)
#define CSL_SYS_INTGEN_INT_ARM1_SETINT   (0x00000001u)

#define CSL_SYS_INTGEN_INT_ARM0_MASK     (0x00001000u)
#define CSL_SYS_INTGEN_INT_ARM0_SHIFT    (0x0000000Cu)
#define CSL_SYS_INTGEN_INT_ARM0_RESETVAL (0x00000000u)

/*----INT_ARM0 Tokens----*/
#define CSL_SYS_INTGEN_INT_ARM0_NOINT    (0x00000000u)
#define CSL_SYS_INTGEN_INT_ARM0_SETINT   (0x00000001u)

#define CSL_SYS_INTGEN_INT_DSP3_MASK     (0x00000080u)
#define CSL_SYS_INTGEN_INT_DSP3_SHIFT    (0x00000007u)
#define CSL_SYS_INTGEN_INT_DSP3_RESETVAL (0x00000000u)

/*----INT_DSP3 Tokens----*/
#define CSL_SYS_INTGEN_INT_DSP3_NOINT    (0x00000000u)
#define CSL_SYS_INTGEN_INT_DSP3_SETINT   (0x00000001u)

#define CSL_SYS_INTGEN_INT_DSP2_MASK     (0x00000040u)
#define CSL_SYS_INTGEN_INT_DSP2_SHIFT    (0x00000006u)
#define CSL_SYS_INTGEN_INT_DSP2_RESETVAL (0x00000000u)

/*----INT_DSP2 Tokens----*/
#define CSL_SYS_INTGEN_INT_DSP2_NOINT    (0x00000000u)
#define CSL_SYS_INTGEN_INT_DSP2_SETINT   (0x00000001u)

#define CSL_SYS_INTGEN_INT_DSP1_MASK     (0x00000020u)
#define CSL_SYS_INTGEN_INT_DSP1_SHIFT    (0x00000005u)
#define CSL_SYS_INTGEN_INT_DSP1_RESETVAL (0x00000000u)

/*----INT_DSP1 Tokens----*/
#define CSL_SYS_INTGEN_INT_DSP1_NOINT    (0x00000000u)
#define CSL_SYS_INTGEN_INT_DSP1_SETINT   (0x00000001u)

#define CSL_SYS_INTGEN_INT_DSP0_MASK     (0x00000010u)
#define CSL_SYS_INTGEN_INT_DSP0_SHIFT    (0x00000004u)
#define CSL_SYS_INTGEN_INT_DSP0_RESETVAL (0x00000000u)

/*----INT_DSP0 Tokens----*/
#define CSL_SYS_INTGEN_INT_DSP0_NOINT    (0x00000000u)
#define CSL_SYS_INTGEN_INT_DSP0_SETINT   (0x00000001u)

#define CSL_SYS_INTGEN_INT_NMI_MASK      (0x00000001u)
#define CSL_SYS_INTGEN_INT_NMI_SHIFT     (0x00000000u)
#define CSL_SYS_INTGEN_INT_NMI_RESETVAL  (0x00000000u)

/*----INT_NMI Tokens----*/
#define CSL_SYS_INTGEN_INT_NMI_NOINT     (0x00000000u)
#define CSL_SYS_INTGEN_INT_NMI_SETINT    (0x00000001u)

#define CSL_SYS_INTGEN_RESETVAL          (0x00000000u)

/* BOOTCFG */

#define CSL_SYS_BOOTCFG_HPIEN_MASK       (0x20000000u)
#define CSL_SYS_BOOTCFG_HPIEN_SHIFT      (0x0000001Du)
#define CSL_SYS_BOOTCFG_HPIEN_RESETVAL   (0x00000000u)

/*----HPIEN Tokens----*/
#define CSL_SYS_BOOTCFG_HPIEN_DISABLE    (0x00000000u)
#define CSL_SYS_BOOTCFG_HPIEN_ENABLE     (0x00000001u)

#define CSL_SYS_BOOTCFG_BTSEL_MASK       (0x03000000u)
#define CSL_SYS_BOOTCFG_BTSEL_SHIFT      (0x00000018u)
#define CSL_SYS_BOOTCFG_BTSEL_RESETVAL   (0x00000000u)

/*----BTSEL Tokens----*/
#define CSL_SYS_BOOTCFG_BTSEL_ROMNAND    (0x00000000u)
#define CSL_SYS_BOOTCFG_BTSEL_NORFLASH   (0x00000001u)
#define CSL_SYS_BOOTCFG_BTSEL_ROMUHPI    (0x00000002u)
#define CSL_SYS_BOOTCFG_BTSEL_ROMUART0   (0x00000003u)

#define CSL_SYS_BOOTCFG_DSP_BT_MASK      (0x00100000u)
#define CSL_SYS_BOOTCFG_DSP_BT_SHIFT     (0x00000014u)
#define CSL_SYS_BOOTCFG_DSP_BT_RESETVAL  (0x00000000u)

/*----DSP_BT Tokens----*/
#define CSL_SYS_BOOTCFG_DSP_BT_ARMBOOT   (0x00000000u)
#define CSL_SYS_BOOTCFG_DSP_BT_DSPBOOT   (0x00000001u)

#define CSL_SYS_BOOTCFG_8_16_MASK        (0x00000100u)
#define CSL_SYS_BOOTCFG_8_16_SHIFT       (0x00000008u)
#define CSL_SYS_BOOTCFG_8_16_RESETVAL    (0x00000000u)

/*----8_16 Tokens----*/
#define CSL_SYS_BOOTCFG_8_16_8BITS       (0x00000000u)
#define CSL_SYS_BOOTCFG_8_16_16BITS      (0x00000001u)

#define CSL_SYS_BOOTCFG_AEAW_MASK        (0x0000001Fu)
#define CSL_SYS_BOOTCFG_AEAW_SHIFT       (0x00000000u)
#define CSL_SYS_BOOTCFG_AEAW_RESETVAL    (0x00000000u)

#define CSL_SYS_BOOTCFG_RESETVAL         (0x00000000u)

/* VDD1P0V_ADJ */

#define CSL_SYS_VDD1P0V_ADJ_VDD1P0V_ADJ_MASK (0x0000000Fu)
#define CSL_SYS_VDD1P0V_ADJ_VDD1P0V_ADJ_SHIFT (0x00000000u)
#define CSL_SYS_VDD1P0V_ADJ_VDD1P0V_ADJ_RESETVAL (0x00000000u)

#define CSL_SYS_VDD1P0V_ADJ_RESETVAL     (0x00000000u)

/* VDD1P2V_ADJ */

#define CSL_SYS_VDD1P2V_ADJ_VDD1P2V_ADJ_MASK (0x0000000Fu)
#define CSL_SYS_VDD1P2V_ADJ_VDD1P2V_ADJ_SHIFT (0x00000000u)
#define CSL_SYS_VDD1P2V_ADJ_VDD1P2V_ADJ_RESETVAL (0x00000000u)

#define CSL_SYS_VDD1P2V_ADJ_RESETVAL     (0x00000000u)

/* DDR_SLEW */

#define CSL_SYS_DDR_SLEW_DDRDATA_SLEW_MASK (0x0000000Cu)
#define CSL_SYS_DDR_SLEW_DDRDATA_SLEW_SHIFT (0x00000002u)
#define CSL_SYS_DDR_SLEW_DDRDATA_SLEW_RESETVAL (0x00000000u)

#define CSL_SYS_DDR_SLEW_DDRCMD_SLEW_MASK (0x00000003u)
#define CSL_SYS_DDR_SLEW_DDRCMD_SLEW_SHIFT (0x00000000u)
#define CSL_SYS_DDR_SLEW_DDRCMD_SLEW_RESETVAL (0x00000000u)

#define CSL_SYS_DDR_SLEW_RESETVAL        (0x00000000u)

/* MV_ENABLE */

#define CSL_SYS_MV_ENABLE_MV_ENABLE_MASK (0x00000001u)
#define CSL_SYS_MV_ENABLE_MV_ENABLE_SHIFT (0x00000000u)
#define CSL_SYS_MV_ENABLE_MV_ENABLE_RESETVAL (0x00000000u)

/*----MV_ENABLE Tokens----*/
#define CSL_SYS_MV_ENABLE_MV_ENABLE_DISABLE (0x00000000u)
#define CSL_SYS_MV_ENABLE_MV_ENABLE_ENABLE (0x00000001u)

#define CSL_SYS_MV_ENABLE_RESETVAL       (0x00000000u)

/* OHCI1394EN */

#define CSL_SYS_OHCI1394EN_1394EN_MASK   (0x00000001u)
#define CSL_SYS_OHCI1394EN_1394EN_SHIFT  (0x00000000u)
#define CSL_SYS_OHCI1394EN_1394EN_RESETVAL (0x00000000u)

/*----1394EN Tokens----*/
#define CSL_SYS_OHCI1394EN_1394EN_DISABLE (0x00000000u)
#define CSL_SYS_OHCI1394EN_1394EN_ENABLE (0x00000001u)

#define CSL_SYS_OHCI1394EN_RESETVAL      (0x00000000u)

/* DAC_DEMEN */

#define CSL_SYS_DAC_DEMEN_DAC_DMEN_MASK  (0x00000001u)
#define CSL_SYS_DAC_DEMEN_DAC_DMEN_SHIFT (0x00000000u)