cslr_gpio.h

ccs下对dm6446的测试程序

#define CSL_GPIO_SET_FAL_TRIG_SETFAL16_MASK (0x00010000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL16_SHIFT (0x00000010u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL16_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL15_MASK (0x00008000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL15_SHIFT (0x0000000Fu)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL15_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL14_MASK (0x00004000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL14_SHIFT (0x0000000Eu)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL14_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL13_MASK (0x00002000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL13_SHIFT (0x0000000Du)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL13_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL12_MASK (0x00001000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL12_SHIFT (0x0000000Cu)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL12_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL11_MASK (0x00000800u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL11_SHIFT (0x0000000Bu)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL11_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL10_MASK (0x00000400u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL10_SHIFT (0x0000000Au)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL10_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL9_MASK (0x00000200u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL9_SHIFT (0x00000009u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL9_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL8_MASK (0x00000100u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL8_SHIFT (0x00000008u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL8_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL7_MASK (0x00000080u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL7_SHIFT (0x00000007u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL7_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL6_MASK (0x00000040u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL6_SHIFT (0x00000006u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL6_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL5_MASK (0x00000020u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL5_SHIFT (0x00000005u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL5_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL4_MASK (0x00000010u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL4_SHIFT (0x00000004u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL4_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL3_MASK (0x00000008u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL3_SHIFT (0x00000003u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL3_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL2_MASK (0x00000004u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL2_SHIFT (0x00000002u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL2_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL1_MASK (0x00000002u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL1_SHIFT (0x00000001u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL1_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL0_MASK (0x00000001u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL0_SHIFT (0x00000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL0_RESETVAL (0x00000000u)

/*----SETFAL Tokens----*/
#define CSL_GPIO_SET_FAL_TRIG_SETFAL_ENABLE (0x00000001u)

#define CSL_GPIO_SET_FAL_TRIG_RESETVAL   (0x00000000u)

/* CLR_FAL_TRIG */

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL31_MASK (0x80000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL31_SHIFT (0x0000001Fu)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL31_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL30_MASK (0x40000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL30_SHIFT (0x0000001Eu)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL30_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL29_MASK (0x20000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL29_SHIFT (0x0000001Du)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL29_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL28_MASK (0x10000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL28_SHIFT (0x0000001Cu)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL28_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL27_MASK (0x08000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL27_SHIFT (0x0000001Bu)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL27_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL26_MASK (0x04000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL26_SHIFT (0x0000001Au)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL26_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL25_MASK (0x02000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL25_SHIFT (0x00000019u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL25_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL24_MASK (0x01000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL24_SHIFT (0x00000018u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL24_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL23_MASK (0x00800000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL23_SHIFT (0x00000017u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL23_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL22_MASK (0x00400000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL22_SHIFT (0x00000016u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL22_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL21_MASK (0x00200000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL21_SHIFT (0x00000015u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL21_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL20_MASK (0x00100000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL20_SHIFT (0x00000014u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL20_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL19_MASK (0x00080000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL19_SHIFT (0x00000013u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL19_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL18_MASK (0x00040000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL18_SHIFT (0x00000012u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL18_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL17_MASK (0x00020000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL17_SHIFT (0x00000011u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL17_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL16_MASK (0x00010000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL16_SHIFT (0x00000010u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL16_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL15_MASK (0x00008000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL15_SHIFT (0x0000000Fu)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL15_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL14_MASK (0x00004000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL14_SHIFT (0x0000000Eu)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL14_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL13_MASK (0x00002000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL13_SHIFT (0x0000000Du)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL13_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL12_MASK (0x00001000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL12_SHIFT (0x0000000Cu)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL12_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL11_MASK (0x00000800u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL11_SHIFT (0x0000000Bu)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL11_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL10_MASK (0x00000400u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL10_SHIFT (0x0000000Au)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL10_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL9_MASK (0x00000200u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL9_SHIFT (0x00000009u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL9_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL8_MASK (0x00000100u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL8_SHIFT (0x00000008u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL8_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL7_MASK (0x00000080u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL7_SHIFT (0x00000007u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL7_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL6_MASK (0x00000040u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL6_SHIFT (0x00000006u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL6_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL5_MASK (0x00000020u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL5_SHIFT (0x00000005u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL5_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL4_MASK (0x00000010u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL4_SHIFT (0x00000004u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL4_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL3_MASK (0x00000008u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL3_SHIFT (0x00000003u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL3_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL2_MASK (0x00000004u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL2_SHIFT (0x00000002u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL2_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL1_MASK (0x00000002u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL1_SHIFT (0x00000001u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL1_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL0_MASK (0x00000001u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL0_SHIFT (0x00000000u)
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL0_RESETVAL (0x00000001u)

/*----CLRFAL Tokens----*/
#define CSL_GPIO_CLR_FAL_TRIG_CLRFAL_DISABLE (0x00000000u)

#define CSL_GPIO_CLR_FAL_TRIG_RESETVAL   (0x00000001u)

/* INTSTAT */

#define CSL_GPIO_INTSTAT_STAT31_MASK      (0x80000000u)
#define CSL_GPIO_INTSTAT_STAT31_SHIFT    (0x0000001Fu)
#define CSL_GPIO_INTSTAT_STAT31_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT30_MASK      (0x40000000u)
#define CSL_GPIO_INTSTAT_STAT30_SHIFT    (0x0000001Eu)
#define CSL_GPIO_INTSTAT_STAT30_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT29_MASK      (0x20000000u)
#define CSL_GPIO_INTSTAT_STAT29_SHIFT    (0x0000001Du)
#define CSL_GPIO_INTSTAT_STAT29_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT28_MASK      (0x10000000u)
#define CSL_GPIO_INTSTAT_STAT28_SHIFT    (0x0000001Cu)
#define CSL_GPIO_INTSTAT_STAT28_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT27_MASK      (0x08000000u)
#define CSL_GPIO_INTSTAT_STAT27_SHIFT    (0x0000001Bu)
#define CSL_GPIO_INTSTAT_STAT27_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT26_MASK      (0x04000000u)
#define CSL_GPIO_INTSTAT_STAT26_SHIFT    (0x0000001Au)
#define CSL_GPIO_INTSTAT_STAT26_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT25_MASK      (0x02000000u)
#define CSL_GPIO_INTSTAT_STAT25_SHIFT    (0x00000019u)
#define CSL_GPIO_INTSTAT_STAT25_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT24_MASK      (0x01000000u)
#define CSL_GPIO_INTSTAT_STAT24_SHIFT    (0x00000018u)
#define CSL_GPIO_INTSTAT_STAT24_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT23_MASK      (0x00800000u)
#define CSL_GPIO_INTSTAT_STAT23_SHIFT    (0x00000017u)
#define CSL_GPIO_INTSTAT_STAT23_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT22_MASK      (0x00400000u)
#define CSL_GPIO_INTSTAT_STAT22_SHIFT    (0x00000016u)
#define CSL_GPIO_INTSTAT_STAT22_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT21_MASK      (0x00200000u)
#define CSL_GPIO_INTSTAT_STAT21_SHIFT    (0x00000015u)
#define CSL_GPIO_INTSTAT_STAT21_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT20_MASK      (0x00100000u)
#define CSL_GPIO_INTSTAT_STAT20_SHIFT    (0x00000014u)
#define CSL_GPIO_INTSTAT_STAT20_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT19_MASK      (0x00080000u)
#define CSL_GPIO_INTSTAT_STAT19_SHIFT    (0x00000013u)
#define CSL_GPIO_INTSTAT_STAT19_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT18_MASK      (0x00040000u)
#define CSL_GPIO_INTSTAT_STAT18_SHIFT    (0x00000012u)
#define CSL_GPIO_INTSTAT_STAT18_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT17_MASK      (0x00020000u)
#define CSL_GPIO_INTSTAT_STAT17_SHIFT    (0x00000011u)
#define CSL_GPIO_INTSTAT_STAT17_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT16_MASK      (0x00010000u)
#define CSL_GPIO_INTSTAT_STAT16_SHIFT    (0x00000010u)
#define CSL_GPIO_INTSTAT_STAT16_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT15_MASK      (0x00008000u)
#define CSL_GPIO_INTSTAT_STAT15_SHIFT    (0x0000000Fu)
#define CSL_GPIO_INTSTAT_STAT15_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT14_MASK      (0x00004000u)
#define CSL_GPIO_INTSTAT_STAT14_SHIFT    (0x0000000Eu)
#define CSL_GPIO_INTSTAT_STAT14_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT13_MASK      (0x00002000u)
#define CSL_GPIO_INTSTAT_STAT13_SHIFT    (0x0000000Du)
#define CSL_GPIO_INTSTAT_STAT13_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT12_MASK      (0x00001000u)
#define CSL_GPIO_INTSTAT_STAT12_SHIFT    (0x0000000Cu)
#define CSL_GPIO_INTSTAT_STAT12_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT11_MASK      (0x00000800u)
#define CSL_GPIO_INTSTAT_STAT11_SHIFT    (0x0000000Bu)
#define CSL_GPIO_INTSTAT_STAT11_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT10_MASK      (0x00000400u)
#define CSL_GPIO_INTSTAT_STAT10_SHIFT    (0x0000000Au)
#define CSL_GPIO_INTSTAT_STAT10_RESETVAL  (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT9_MASK       (0x00000200u)
#define CSL_GPIO_INTSTAT_STAT9_SHIFT     (0x00000009u)
#define CSL_GPIO_INTSTAT_STAT9_RESETVAL   (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT8_MASK       (0x00000100u)
#define CSL_GPIO_INTSTAT_STAT8_SHIFT     (0x00000008u)
#define CSL_GPIO_INTSTAT_STAT8_RESETVAL   (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT7_MASK       (0x00000080u)
#define CSL_GPIO_INTSTAT_STAT7_SHIFT     (0x00000007u)
#define CSL_GPIO_INTSTAT_STAT7_RESETVAL   (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT6_MASK       (0x00000040u)
#define CSL_GPIO_INTSTAT_STAT6_SHIFT     (0x00000006u)
#define CSL_GPIO_INTSTAT_STAT6_RESETVAL   (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT5_MASK       (0x00000020u)
#define CSL_GPIO_INTSTAT_STAT5_SHIFT     (0x00000005u)
#define CSL_GPIO_INTSTAT_STAT5_RESETVAL   (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT4_MASK       (0x00000010u)
#define CSL_GPIO_INTSTAT_STAT4_SHIFT     (0x00000004u)
#define CSL_GPIO_INTSTAT_STAT4_RESETVAL   (0x00000000u)

#define CSL_GPIO_INTSTAT_STAT3_MASK       (0x