cslr_gpio.h

ccs下对dm6446的测试程序

#define CSL_GPIO_SET_RIS_TRIG_SETRIS30_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS29_MASK (0x20000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS29_SHIFT (0x0000001Du)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS29_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS28_MASK (0x10000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS28_SHIFT (0x0000001Cu)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS28_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS27_MASK (0x08000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS27_SHIFT (0x0000001Bu)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS27_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS26_MASK (0x04000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS26_SHIFT (0x0000001Au)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS26_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS25_MASK (0x02000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS25_SHIFT (0x00000019u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS25_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS24_MASK (0x01000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS24_SHIFT (0x00000018u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS24_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS23_MASK (0x00800000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS23_SHIFT (0x00000017u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS23_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS22_MASK (0x00400000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS22_SHIFT (0x00000016u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS22_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS21_MASK (0x00200000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS21_SHIFT (0x00000015u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS21_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS20_MASK (0x00100000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS20_SHIFT (0x00000014u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS20_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS19_MASK (0x00080000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS19_SHIFT (0x00000013u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS19_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS18_MASK (0x00040000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS18_SHIFT (0x00000012u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS18_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS17_MASK (0x00020000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS17_SHIFT (0x00000011u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS17_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS16_MASK (0x00010000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS16_SHIFT (0x00000010u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS16_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS15_MASK (0x00008000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS15_SHIFT (0x0000000Fu)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS15_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS14_MASK (0x00004000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS14_SHIFT (0x0000000Eu)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS14_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS13_MASK (0x00002000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS13_SHIFT (0x0000000Du)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS13_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS12_MASK (0x00001000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS12_SHIFT (0x0000000Cu)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS12_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS11_MASK (0x00000800u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS11_SHIFT (0x0000000Bu)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS11_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS10_MASK (0x00000400u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS10_SHIFT (0x0000000Au)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS10_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS9_MASK (0x00000200u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS9_SHIFT (0x00000009u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS9_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS8_MASK (0x00000100u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS8_SHIFT (0x00000008u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS8_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS7_MASK (0x00000080u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS7_SHIFT (0x00000007u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS7_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS6_MASK (0x00000040u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS6_SHIFT (0x00000006u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS6_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS5_MASK (0x00000020u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS5_SHIFT (0x00000005u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS5_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS4_MASK (0x00000010u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS4_SHIFT (0x00000004u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS4_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS3_MASK (0x00000008u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS3_SHIFT (0x00000003u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS3_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS2_MASK (0x00000004u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS2_SHIFT (0x00000002u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS2_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS1_MASK (0x00000002u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS1_SHIFT (0x00000001u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS1_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_RIS_TRIG_SETRIS0_MASK (0x00000001u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS0_SHIFT (0x00000000u)
#define CSL_GPIO_SET_RIS_TRIG_SETRIS0_RESETVAL (0x00000000u)

/*----SETRIS Tokens----*/
#define CSL_GPIO_SET_RIS_TRIG_SETRIS_ENABLE (0x00000001u)

#define CSL_GPIO_SET_RIS_TRIG_RESETVAL   (0x00000000u)

/* CLR_RIS_TRIG */

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS31_MASK (0x80000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS31_SHIFT (0x0000001Fu)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS31_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS30_MASK (0x40000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS30_SHIFT (0x0000001Eu)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS30_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS29_MASK (0x20000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS29_SHIFT (0x0000001Du)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS29_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS28_MASK (0x10000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS28_SHIFT (0x0000001Cu)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS28_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS27_MASK (0x08000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS27_SHIFT (0x0000001Bu)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS27_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS26_MASK (0x04000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS26_SHIFT (0x0000001Au)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS26_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS25_MASK (0x02000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS25_SHIFT (0x00000019u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS25_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS24_MASK (0x01000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS24_SHIFT (0x00000018u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS24_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS23_MASK (0x00800000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS23_SHIFT (0x00000017u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS23_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS22_MASK (0x00400000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS22_SHIFT (0x00000016u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS22_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS21_MASK (0x00200000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS21_SHIFT (0x00000015u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS21_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS20_MASK (0x00100000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS20_SHIFT (0x00000014u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS20_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS19_MASK (0x00080000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS19_SHIFT (0x00000013u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS19_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS18_MASK (0x00040000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS18_SHIFT (0x00000012u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS18_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS17_MASK (0x00020000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS17_SHIFT (0x00000011u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS17_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS16_MASK (0x00010000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS16_SHIFT (0x00000010u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS16_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS15_MASK (0x00008000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS15_SHIFT (0x0000000Fu)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS15_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS14_MASK (0x00004000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS14_SHIFT (0x0000000Eu)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS14_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS13_MASK (0x00002000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS13_SHIFT (0x0000000Du)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS13_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS12_MASK (0x00001000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS12_SHIFT (0x0000000Cu)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS12_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS11_MASK (0x00000800u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS11_SHIFT (0x0000000Bu)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS11_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS10_MASK (0x00000400u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS10_SHIFT (0x0000000Au)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS10_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS9_MASK (0x00000200u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS9_SHIFT (0x00000009u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS9_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS8_MASK (0x00000100u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS8_SHIFT (0x00000008u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS8_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS7_MASK (0x00000080u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS7_SHIFT (0x00000007u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS7_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS6_MASK (0x00000040u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS6_SHIFT (0x00000006u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS6_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS5_MASK (0x00000020u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS5_SHIFT (0x00000005u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS5_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS4_MASK (0x00000010u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS4_SHIFT (0x00000004u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS4_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS3_MASK (0x00000008u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS3_SHIFT (0x00000003u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS3_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS2_MASK (0x00000004u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS2_SHIFT (0x00000002u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS2_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS1_MASK (0x00000002u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS1_SHIFT (0x00000001u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS1_RESETVAL (0x00000001u)

#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS0_MASK (0x00000001u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS0_SHIFT (0x00000000u)
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS0_RESETVAL (0x00000001u)

/*----CLRRIS Tokens----*/
#define CSL_GPIO_CLR_RIS_TRIG_CLRRIS_DISABLE (0x00000000u)

#define CSL_GPIO_CLR_RIS_TRIG_RESETVAL   (0x00000001u)

/* SET_FAL_TRIG */

#define CSL_GPIO_SET_FAL_TRIG_SETFAL31_MASK (0x80000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL31_SHIFT (0x0000001Fu)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL31_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL30_MASK (0x40000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL30_SHIFT (0x0000001Eu)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL30_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL29_MASK (0x20000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL29_SHIFT (0x0000001Du)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL29_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL28_MASK (0x10000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL28_SHIFT (0x0000001Cu)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL28_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL27_MASK (0x08000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL27_SHIFT (0x0000001Bu)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL27_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL26_MASK (0x04000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL26_SHIFT (0x0000001Au)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL26_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL25_MASK (0x02000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL25_SHIFT (0x00000019u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL25_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL24_MASK (0x01000000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL24_SHIFT (0x00000018u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL24_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL23_MASK (0x00800000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL23_SHIFT (0x00000017u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL23_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL22_MASK (0x00400000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL22_SHIFT (0x00000016u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL22_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL21_MASK (0x00200000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL21_SHIFT (0x00000015u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL21_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL20_MASK (0x00100000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL20_SHIFT (0x00000014u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL20_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL19_MASK (0x00080000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL19_SHIFT (0x00000013u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL19_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL18_MASK (0x00040000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL18_SHIFT (0x00000012u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL18_RESETVAL (0x00000000u)

#define CSL_GPIO_SET_FAL_TRIG_SETFAL17_MASK (0x00020000u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL17_SHIFT (0x00000011u)
#define CSL_GPIO_SET_FAL_TRIG_SETFAL17_RESETVAL (0x00000000u)