📄 cslr_emif.h
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/* ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
*
* Use of this software is controlled by the terms and conditions found in the
* license agreement under which this software has been supplied.
* ===========================================================================
*/
#ifndef _CSLR_EMIF_H_
#define _CSLR_EMIF_H_
/** @file cslr_emif.h
*
* @brief This file contains the Register Desciptions for EMIF
*
* Path: \\(CSLPATH)\\soc\\davinci\\arm9\\src
*
*********************************************************************/
/* =============================================================================
* Revision History
* ===============
* 02-09-2004 brn File Updated for the new CSL architecture
* =============================================================================
*/
#include <cslr.h>
#include <tistdtypes.h>
/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct {
volatile Uint32 ERCSR;
volatile Uint32 AWCCR;
volatile Uint32 SDBCR;
volatile Uint32 SDRCR;
volatile Uint32 AB1CR;
volatile Uint32 AB2CR;
volatile Uint32 AB3CR;
volatile Uint32 AB4CR;
volatile Uint32 SDTIMR;
volatile Uint32 DDRSR;
volatile Uint32 DDRPHYCR;
volatile Uint32 DDRPHYSR;
volatile Uint32 TOTAR;
volatile Uint32 TOTACTR;
volatile Uint32 DDRPHYID_REV;
volatile Uint32 SDSRETR;
volatile Uint32 EIRR;
volatile Uint32 EIMR;
volatile Uint32 EIMSR;
volatile Uint32 EIMCR;
volatile Uint32 IOCTRLR;
volatile Uint32 IOSTATR;
volatile Uint8 RSVD0[8];
volatile Uint32 NANDFCR;
volatile Uint32 NANDFSR;
volatile Uint8 RSVD1[8];
volatile Uint32 NANDF1ECC;
volatile Uint32 NANDF2ECC;
volatile Uint32 NANDF3ECC;
volatile Uint32 NANDF4ECC;
} CSL_EmifRegs;
/**************************************************************************\
* Overlay structure typedef definition
\**************************************************************************/
typedef volatile CSL_EmifRegs *CSL_EmifRegsOvly;
/**************************************************************************\
* Field Definition Macros
\**************************************************************************/
/* ERCSR */
#define CSL_EMIF_ERCSR_BE_MASK (0x80000000u)
#define CSL_EMIF_ERCSR_BE_SHIFT (0x0000001Fu)
#define CSL_EMIF_ERCSR_BE_RESETVAL (0x00000001u)
#define CSL_EMIF_ERCSR_FR_MASK (0x40000000u)
#define CSL_EMIF_ERCSR_FR_SHIFT (0x0000001Eu)
#define CSL_EMIF_ERCSR_FR_RESETVAL (0x00000001u)
#define CSL_EMIF_ERCSR_MID_MASK (0x3FFF0000u)
#define CSL_EMIF_ERCSR_MID_SHIFT (0x00000010u)
#define CSL_EMIF_ERCSR_MID_RESETVAL (0x00000000u)
#define CSL_EMIF_ERCSR_MAJREV_MASK (0x0000FF00u)
#define CSL_EMIF_ERCSR_MAJREV_SHIFT (0x00000008u)
#define CSL_EMIF_ERCSR_MAJREV_RESETVAL (0x00000002u)
#define CSL_EMIF_ERCSR_MINREV_MASK (0x000000FFu)
#define CSL_EMIF_ERCSR_MINREV_SHIFT (0x00000000u)
#define CSL_EMIF_ERCSR_MINREV_RESETVAL (0x00000001u)
#define CSL_EMIF_ERCSR_RESETVAL (0xC0000201u)
/* AWCCR */
#define CSL_EMIF_AWCCR_WP3_MASK (0x80000000u)
#define CSL_EMIF_AWCCR_WP3_SHIFT (0x0000001Fu)
#define CSL_EMIF_AWCCR_WP3_RESETVAL (0x00000001u)
/*----WP3 Tokens----*/
#define CSL_EMIF_AWCCR_WP3_WAITLOW (0x00000000u)
#define CSL_EMIF_AWCCR_WP3_WAITHIGH (0x00000001u)
#define CSL_EMIF_AWCCR_WP2_MASK (0x40000000u)
#define CSL_EMIF_AWCCR_WP2_SHIFT (0x0000001Eu)
#define CSL_EMIF_AWCCR_WP2_RESETVAL (0x00000001u)
/*----WP2 Tokens----*/
#define CSL_EMIF_AWCCR_WP2_WAITLOW (0x00000000u)
#define CSL_EMIF_AWCCR_WP2_WAITHIGH (0x00000001u)
#define CSL_EMIF_AWCCR_WP1_MASK (0x20000000u)
#define CSL_EMIF_AWCCR_WP1_SHIFT (0x0000001Du)
#define CSL_EMIF_AWCCR_WP1_RESETVAL (0x00000001u)
/*----WP1 Tokens----*/
#define CSL_EMIF_AWCCR_WP1_WAITLOW (0x00000000u)
#define CSL_EMIF_AWCCR_WP1_WAITHIGH (0x00000001u)
#define CSL_EMIF_AWCCR_WP0_MASK (0x10000000u)
#define CSL_EMIF_AWCCR_WP0_SHIFT (0x0000001Cu)
#define CSL_EMIF_AWCCR_WP0_RESETVAL (0x00000001u)
/*----WP0 Tokens----*/
#define CSL_EMIF_AWCCR_WP0_WAITLOW (0x00000000u)
#define CSL_EMIF_AWCCR_WP0_WAITHIGH (0x00000001u)
#define CSL_EMIF_AWCCR_CS3WAIT_MASK (0x00C00000u)
#define CSL_EMIF_AWCCR_CS3WAIT_SHIFT (0x00000016u)
#define CSL_EMIF_AWCCR_CS3WAIT_RESETVAL (0x00000000u)
#define CSL_EMIF_AWCCR_CS2WAIT_MASK (0x00300000u)
#define CSL_EMIF_AWCCR_CS2WAIT_SHIFT (0x00000014u)
#define CSL_EMIF_AWCCR_CS2WAIT_RESETVAL (0x00000000u)
#define CSL_EMIF_AWCCR_CS1WAIT_MASK (0x000C0000u)
#define CSL_EMIF_AWCCR_CS1WAIT_SHIFT (0x00000012u)
#define CSL_EMIF_AWCCR_CS1WAIT_RESETVAL (0x00000000u)
#define CSL_EMIF_AWCCR_CS0WAIT_MASK (0x00030000u)
#define CSL_EMIF_AWCCR_CS0WAIT_SHIFT (0x00000010u)
#define CSL_EMIF_AWCCR_CS0WAIT_RESETVAL (0x00000000u)
#define CSL_EMIF_AWCCR_MEWC_MASK (0x000000FFu)
#define CSL_EMIF_AWCCR_MEWC_SHIFT (0x00000000u)
#define CSL_EMIF_AWCCR_MEWC_RESETVAL (0x00000080u)
#define CSL_EMIF_AWCCR_RESETVAL (0xF0000080u)
/* SDBCR */
#define CSL_EMIF_SDBCR_SR_MASK (0x80000000u)
#define CSL_EMIF_SDBCR_SR_SHIFT (0x0000001Fu)
#define CSL_EMIF_SDBCR_SR_RESETVAL (0x00000000u)
#define CSL_EMIF_SDBCR_PD_MASK (0x40000000u)
#define CSL_EMIF_SDBCR_PD_SHIFT (0x0000001Eu)
#define CSL_EMIF_SDBCR_PD_RESETVAL (0x00000000u)
#define CSL_EMIF_SDBCR_PDWR_MASK (0x20000000u)
#define CSL_EMIF_SDBCR_PDWR_SHIFT (0x0000001Du)
#define CSL_EMIF_SDBCR_PDWR_RESETVAL (0x00000000u)
#define CSL_EMIF_SDBCR_DDRDRST_MASK (0x00020000u)
#define CSL_EMIF_SDBCR_DDRDRST_SHIFT (0x00000011u)
#define CSL_EMIF_SDBCR_DDRDRST_RESETVAL (0x00000000u)
#define CSL_EMIF_SDBCR_BIT17LOCK_MASK (0x00010000u)
#define CSL_EMIF_SDBCR_BIT17LOCK_SHIFT (0x00000010u)
#define CSL_EMIF_SDBCR_BIT17LOCK_RESETVAL (0x00000000u)
#define CSL_EMIF_SDBCR_NM_MASK (0x00004000u)
#define CSL_EMIF_SDBCR_NM_SHIFT (0x0000000Eu)
#define CSL_EMIF_SDBCR_NM_RESETVAL (0x00000000u)
#define CSL_EMIF_SDBCR_DISDDRDLL_MASK (0x00002000u)
#define CSL_EMIF_SDBCR_DISDDRDLL_SHIFT (0x0000000Du)
#define CSL_EMIF_SDBCR_DISDDRDLL_RESETVAL (0x00000001u)
#define CSL_EMIF_SDBCR_BIT13LOCK_MASK (0x00001000u)
#define CSL_EMIF_SDBCR_BIT13LOCK_SHIFT (0x0000000Cu)
#define CSL_EMIF_SDBCR_BIT13LOCK_RESETVAL (0x00000000u)
#define CSL_EMIF_SDBCR_CL_MASK (0x00000E00u)
#define CSL_EMIF_SDBCR_CL_SHIFT (0x00000009u)
#define CSL_EMIF_SDBCR_CL_RESETVAL (0x00000003u)
/*----CL Tokens----*/
#define CSL_EMIF_SDBCR_CL_CASLAT2 (0x00000002u)
#define CSL_EMIF_SDBCR_BIT11_9LOCK_MASK (0x00000100u)
#define CSL_EMIF_SDBCR_BIT11_9LOCK_SHIFT (0x00000008u)
#define CSL_EMIF_SDBCR_BIT11_9LOCK_RESETVAL (0x00000000u)
#define CSL_EMIF_SDBCR_IBANK_MASK (0x00000070u)
#define CSL_EMIF_SDBCR_IBANK_SHIFT (0x00000004u)
#define CSL_EMIF_SDBCR_IBANK_RESETVAL (0x00000002u)
/*----IBANK Tokens----*/
#define CSL_EMIF_SDBCR_IBANK_SD1BANK (0x00000000u)
#define CSL_EMIF_SDBCR_EBANK_MASK (0x00000008u)
#define CSL_EMIF_SDBCR_EBANK_SHIFT (0x00000003u)
#define CSL_EMIF_SDBCR_EBANK_RESETVAL (0x00000000u)
#define CSL_EMIF_SDBCR_PAGESIZE_MASK (0x00000007u)
#define CSL_EMIF_SDBCR_PAGESIZE_SHIFT (0x00000000u)
#define CSL_EMIF_SDBCR_PAGESIZE_RESETVAL (0x00000000u)
#define CSL_EMIF_SDBCR_RESETVAL (0x00000620u)
/* SDRCR */
#define CSL_EMIF_SDRCR_DDRRT_MASK (0x00070000u)
#define CSL_EMIF_SDRCR_DDRRT_SHIFT (0x00000010u)
#define CSL_EMIF_SDRCR_DDRRT_RESETVAL (0x00000000u)
#define CSL_EMIF_SDRCR_RR_MASK (0x00001FFFu)
#define CSL_EMIF_SDRCR_RR_SHIFT (0x00000000u)
#define CSL_EMIF_SDRCR_RR_RESETVAL (0x00000010u)
#define CSL_EMIF_SDRCR_RESETVAL (0x00000010u)
/* AB1CR */
#define CSL_EMIF_AB1CR_SS_MASK (0x80000000u)
#define CSL_EMIF_AB1CR_SS_SHIFT (0x0000001Fu)
#define CSL_EMIF_AB1CR_SS_RESETVAL (0x00000000u)
#define CSL_EMIF_AB1CR_EW_MASK (0x40000000u)
#define CSL_EMIF_AB1CR_EW_SHIFT (0x0000001Eu)
#define CSL_EMIF_AB1CR_EW_RESETVAL (0x00000000u)
#define CSL_EMIF_AB1CR_W_SETUP_MASK (0x3C000000u)
#define CSL_EMIF_AB1CR_W_SETUP_SHIFT (0x0000001Au)
#define CSL_EMIF_AB1CR_W_SETUP_RESETVAL (0x0000000Fu)
#define CSL_EMIF_AB1CR_W_STROBE_MASK (0x03F00000u)
#define CSL_EMIF_AB1CR_W_STROBE_SHIFT (0x00000014u)
#define CSL_EMIF_AB1CR_W_STROBE_RESETVAL (0x0000003Fu)
#define CSL_EMIF_AB1CR_W_HOLD_MASK (0x000E0000u)
#define CSL_EMIF_AB1CR_W_HOLD_SHIFT (0x00000011u)
#define CSL_EMIF_AB1CR_W_HOLD_RESETVAL (0x00000007u)
#define CSL_EMIF_AB1CR_R_SETUP_MASK (0x0001E000u)
#define CSL_EMIF_AB1CR_R_SETUP_SHIFT (0x0000000Du)
#define CSL_EMIF_AB1CR_R_SETUP_RESETVAL (0x0000000Fu)
#define CSL_EMIF_AB1CR_R_STROBE_MASK (0x00001F80u)
#define CSL_EMIF_AB1CR_R_STROBE_SHIFT (0x00000007u)
#define CSL_EMIF_AB1CR_R_STROBE_RESETVAL (0x0000003Fu)
#define CSL_EMIF_AB1CR_R_HOLD_MASK (0x00000070u)
#define CSL_EMIF_AB1CR_R_HOLD_SHIFT (0x00000004u)
#define CSL_EMIF_AB1CR_R_HOLD_RESETVAL (0x00000007u)
#define CSL_EMIF_AB1CR_TA_MASK (0x0000000Cu)
#define CSL_EMIF_AB1CR_TA_SHIFT (0x00000002u)
#define CSL_EMIF_AB1CR_TA_RESETVAL (0x00000003u)
#define CSL_EMIF_AB1CR_ASIZE_MASK (0x00000003u)
#define CSL_EMIF_AB1CR_ASIZE_SHIFT (0x00000000u)
#define CSL_EMIF_AB1CR_ASIZE_RESETVAL (0x00000001u)
/*----ASIZE Tokens----*/
#define CSL_EMIF_AB1CR_ASIZE_ASIZE_8BITS (0x00000000u)
#define CSL_EMIF_AB1CR_ASIZE_ASIZE_16BITS (0x00000001u)
#define CSL_EMIF_AB1CR_RESETVAL (0x3FFFFFFDu)
/* AB2CR */
#define CSL_EMIF_AB2CR_SS_MASK (0x80000000u)
#define CSL_EMIF_AB2CR_SS_SHIFT (0x0000001Fu)
#define CSL_EMIF_AB2CR_SS_RESETVAL (0x00000000u)
#define CSL_EMIF_AB2CR_EW_MASK (0x40000000u)
#define CSL_EMIF_AB2CR_EW_SHIFT (0x0000001Eu)
#define CSL_EMIF_AB2CR_EW_RESETVAL (0x00000000u)
#define CSL_EMIF_AB2CR_W_SETUP_MASK (0x3C000000u)
#define CSL_EMIF_AB2CR_W_SETUP_SHIFT (0x0000001Au)
#define CSL_EMIF_AB2CR_W_SETUP_RESETVAL (0x0000000Fu)
#define CSL_EMIF_AB2CR_W_STROBE_MASK (0x03F00000u)
#define CSL_EMIF_AB2CR_W_STROBE_SHIFT (0x00000014u)
#define CSL_EMIF_AB2CR_W_STROBE_RESETVAL (0x0000003Fu)
#define CSL_EMIF_AB2CR_W_HOLD_MASK (0x000E0000u)
#define CSL_EMIF_AB2CR_W_HOLD_SHIFT (0x00000011u)
#define CSL_EMIF_AB2CR_W_HOLD_RESETVAL (0x00000007u)
#define CSL_EMIF_AB2CR_R_SETUP_MASK (0x0001E000u)
#define CSL_EMIF_AB2CR_R_SETUP_SHIFT (0x0000000Du)
#define CSL_EMIF_AB2CR_R_SETUP_RESETVAL (0x0000000Fu)
#define CSL_EMIF_AB2CR_R_STROBE_MASK (0x00001F80u)
#define CSL_EMIF_AB2CR_R_STROBE_SHIFT (0x00000007u)
#define CSL_EMIF_AB2CR_R_STROBE_RESETVAL (0x0000003Fu)
#define CSL_EMIF_AB2CR_R_HOLD_MASK (0x00000070u)
#define CSL_EMIF_AB2CR_R_HOLD_SHIFT (0x00000004u)
#define CSL_EMIF_AB2CR_R_HOLD_RESETVAL (0x00000007u)
#define CSL_EMIF_AB2CR_TA_MASK (0x0000000Cu)
#define CSL_EMIF_AB2CR_TA_SHIFT (0x00000002u)
#define CSL_EMIF_AB2CR_TA_RESETVAL (0x00000003u)
#define CSL_EMIF_AB2CR_ASIZE_MASK (0x00000003u)
#define CSL_EMIF_AB2CR_ASIZE_SHIFT (0x00000000u)
#define CSL_EMIF_AB2CR_ASIZE_RESETVAL (0x00000001u)
/*----ASIZE Tokens----*/
#define CSL_EMIF_AB2CR_ASIZE_ASIZE_8BITS (0x00000000u)
#define CSL_EMIF_AB2CR_ASIZE_ASIZE_16BITS (0x00000001u)
#define CSL_EMIF_AB2CR_RESETVAL (0x3FFFFFFDu)
/* AB3CR */
#define CSL_EMIF_AB3CR_SS_MASK (0x80000000u)
#define CSL_EMIF_AB3CR_SS_SHIFT (0x0000001Fu)
#define CSL_EMIF_AB3CR_SS_RESETVAL (0x00000000u)
#define CSL_EMIF_AB3CR_EW_MASK (0x40000000u)
#define CSL_EMIF_AB3CR_EW_SHIFT (0x0000001Eu)
#define CSL_EMIF_AB3CR_EW_RESETVAL (0x00000000u)
#define CSL_EMIF_AB3CR_W_SETUP_MASK (0x3C000000u)
#define CSL_EMIF_AB3CR_W_SETUP_SHIFT (0x0000001Au)
#define CSL_EMIF_AB3CR_W_SETUP_RESETVAL (0x0000000Fu)
#define CSL_EMIF_AB3CR_W_STROBE_MASK (0x03F00000u)
#define CSL_EMIF_AB3CR_W_STROBE_SHIFT (0x00000014u)
#define CSL_EMIF_AB3CR_W_STROBE_RESETVAL (0x0000003Fu)
#define CSL_EMIF_AB3CR_W_HOLD_MASK (0x000E0000u)
#define CSL_EMIF_AB3CR_W_HOLD_SHIFT (0x00000011u)
#define CSL_EMIF_AB3CR_W_HOLD_RESETVAL (0x00000007u)
#define CSL_EMIF_AB3CR_R_SETUP_MASK (0x0001E000u)
#define CSL_EMIF_AB3CR_R_SETUP_SHIFT (0x0000000Du)
#define CSL_EMIF_AB3CR_R_SETUP_RESETVAL (0x0000000Fu)
#define CSL_EMIF_AB3CR_R_STROBE_MASK (0x00001F80u)
#define CSL_EMIF_AB3CR_R_STROBE_SHIFT (0x00000007u)
#define CSL_EMIF_AB3CR_R_STROBE_RESETVAL (0x0000003Fu)
#define CSL_EMIF_AB3CR_R_HOLD_MASK (0x00000070u)
#define CSL_EMIF_AB3CR_R_HOLD_SHIFT (0x00000004u)
#define CSL_EMIF_AB3CR_R_HOLD_RESETVAL (0x00000007u)
#define CSL_EMIF_AB3CR_TA_MASK (0x0000000Cu)
#define CSL_EMIF_AB3CR_TA_SHIFT (0x00000002u)
#define CSL_EMIF_AB3CR_TA_RESETVAL (0x00000003u)
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