smcc67superio.c

仍然是MBX860中的通用配置文件源代码

/* smcC67SuperIo.c - Motorola MBX860 Super I/O chip init. routine */

/* Copyright 1998 Wind River Systems, Inc. */
/* Copyright 1997,1998 Motorola, Inc., All Rights Reserved */

/*
modification history
--------------------
01c,27map98,map code cleanup.
01b,24mar98,rhk changed file name to smcC67SuperIo.c.
01a,18nov97,rhk written, based on file fdc37c67x.s version 01b.
*/

/*
DESCRIPTION

This module initializes an SMC fd37c67 SuperIO chip which supports
a floppy disk controller, two serial ports, a parallel port, IDE registers,
a real-time clock, a keyboard controller and auxillary I/O.

Two IDE register sets are supported by this chip, allowing
up to two IDE controllers (IDE1, IDE2) to be connected, however this module
configures only one (IDE1).

The interrupt levels programmed into this SuperIO chip are from the MBX
Engineering Specification, section 4.13.  The table below shows the function
interrupt levels for the SuperIO and the corresponding levels routed to the ISA
interrupt chip.  These values cannot be changed, they are hardwired from the
SuperIO (S/IO) device into the ISA interrupt chip.

.CS
	Function		S/IO interrupt		ISA interrupt
	-------------------------------------------------------------
	Serial Port 1		INT4			INT4
	Serial Port 2		INT3			INT3
	Floppy Disk Ctrlr	INT7			INT6
	Keyboard		INT10			INT1
	Mouse			INT12			INT12
	Parallel Port		INT11			INT7
.CE

The initialization sequence for each supported device is as follows:
setup the device's base address (in ISA I/O space), its interrupt level,
and any additional features (Eg., DMA channel, mode, options) and then
enable the device.

*/

/* include files */

#include "vxWorks.h"
#include "asm.h"
#include "smcC67SuperIo.h"
#include "mbx800.h"

/* externals */

IMPORT UINT8 sysUioRead();
IMPORT void  sysUioWrite();

#define	C67_READ(devAdrs, reg)		sysUioRead (devAdrs, reg)
#define	C67_WRITE(devAdrs, reg, val)	sysUioWrite (devAdrs, reg, val)

/* globals */

void	smcC67Init ();

/* local definitions */

#define EIEIO_SYNC  __asm__("        eieio;  sync")

/******************************************************************************
*
* smcC67Init - initialize the Super I/O chip
*
* This function performs the necessary initialization of the devices on
* the SMC fdc37c67 Super I/O chip.
*
* Upon completion, UIO resource registers are mapped as follows:
*.CS
*       Resource        Enabled         Address
*       FDC             Yes             PRI     3F0-3F7
*       IDE             Yes             PRI     1F0-1F7 3F6, 3F7
*       UART1           Yes             COM1    3F8-3FF
*       UART2           Yes             COM2    2F8-2FF
*       Parallel PORT   Yes             LPT1    3BC-3BE
*       RTC             Yes                     070, 071
*       KBC             Yes                     060, 064
*       GPIO            Yes                     0EA, 0EB
*.CE
*
* RETURNS: N/A
*/

void smcC67Init (void)
    {
    UINT8	temp;

    /* 
     * store the recognition pattern (config key) into the config.
     * port.  This causes the chip to enter its configuration state.
     */

    * (UINT8 *)(CPU_ISA_C67_BA) = CONFIG_KEY;
    EIEIO_SYNC;
    * (UINT8 *)(CPU_ISA_C67_BA) = CONFIG_KEY;
    EIEIO_SYNC;

    /* enable the appropriate power control and management bits */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_PWR_CTL, C67_PWR_ENBL);
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_PWR_MNG, C67_DISABLE);

    /* initialize and configure the Floppy Disk controller */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_LUN_INDEX, C67_LUN_FDD);

    /* initialize the FDD address */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_PBASE_HI, (ISA_FDC_BA >>8) );
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_PBASE_LO, (ISA_FDC_BA & 0xff));

    /* do the rest of the FDD registers */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_PIRQ_SEL, C67_FDD_INT_LVL); /* IRQ */
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_DMAC_SEL, C67_DMA_CHAN2);  /* DMA */
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_MODE_REG, 
			( C67_PS2_MODE | C67_NON_BURST ) );    /* mode */
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_OPTS_REG, C67_DENSITY_0); /*options*/
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_FDD_TYPE_REG, 0x55);
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_FDD0_REG, 0x01);
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_FDD1_REG, 0x01);

    /* enable the Floppy device */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_ACTIVATE, C67_LUN_ENABLE);

    /* initialize the Parallel Port device */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_LUN_INDEX, C67_LUN_PP);

    /* initialize the PP address */
    
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_PBASE_HI, (ISA_LPT1_BA >>8) );
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_PBASE_LO, (ISA_LPT1_BA & 0xff));
    
    /* do the rest of the parallel port registers */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_PIRQ_SEL, C67_PP_INT_LVL); /* IRQ */
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_DMAC_SEL, C67_NO_DMA);    /* DMA */
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_MODE_REG, C67_PRINTER_MODE); /*mode*/
    
    /* enable the parallel port device */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_ACTIVATE, C67_LUN_ENABLE);

    /* initialize serial port 1 */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_LUN_INDEX, C67_LUN_SP1);

    /* initialize the SP1 address */
    
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_PBASE_HI, (ISA_COM1_BA >>8) );
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_PBASE_LO, (ISA_COM1_BA & 0xff));
    
    /* do the rest of the SP1 registers */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_PIRQ_SEL, C67_SP1_INT_LVL); /* IRQ */
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_MODE_REG, C67_DISABLE);    /* mode */
    
    /* enable the serial port 1 device */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_ACTIVATE, C67_LUN_ENABLE);

    /* initialize serial port 2 */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_LUN_INDEX, C67_LUN_SP2);

    /* initialize the SP2 address */
    
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_PBASE_HI, (ISA_COM2_BA >>8) );
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_PBASE_LO, (ISA_COM2_BA & 0xff));
    
    /* do the rest of the SP2 registers */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_PIRQ_SEL, C67_SP2_INT_LVL); /* IRQ */
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_MODE_REG, C67_DISABLE);    /* mode */
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_OPTS_REG, C67_DISABLE); /* options */ 
    
    /* enable the serial port 2 device */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_ACTIVATE, C67_LUN_ENABLE);

    /* initialize the keyboard controller */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_LUN_INDEX, C67_LUN_KBC);

    /* do the rest of the keyboard registers */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_PIRQ_SEL, C67_KEY_INT_LVL); /* IRQ */
    (void) C67_WRITE (CPU_ISA_C67_BA, C67_SIRQ_SEL, C67_MOU_INT_LVL); /*IRQ 2*/
    
    /* enable the keyboard controller */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_ACTIVATE, C67_LUN_ENABLE);

    /* initialize the AUX I/O */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_LUN_INDEX, C67_LUN_AUX_IO);

    /* enable the AUXIO device */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_ACTIVATE, C67_LUN_ENABLE);

    /* init PIN MUX reg. to enable IRQ11 */

    (void) C67_WRITE (CPU_ISA_C67_BA, C67_PIN_MUX_REG, C67_DISABLE);

    /* check if 93x */

    temp = C67_READ (CPU_ISA_C67_BA, C67_DEV_ID_REG);
    if ( temp == C67_932_DEV)
	{

	/* 
	 * configure the additional features for the super I/O
	 *
	 * initialize IDE1 
	 */

	(void) C67_WRITE (CPU_ISA_C67_BA, C67_LUN_INDEX, C67_LUN_IDE1);

	/* initialize the IDE1 address */
    
	(void) C67_WRITE (CPU_ISA_C67_BA, C67_PBASE_HI, (ISA_IDE_CMND_BA >>8));
	(void) C67_WRITE (CPU_ISA_C67_BA, C67_PBASE_LO, 
			    (ISA_IDE_CMND_BA & 0xff));
	(void) C67_WRITE (CPU_ISA_C67_BA, C67_SBASE_HI, 
		 	    (ISA_IDE_CNTRL_BA >>8));
	(void) C67_WRITE (CPU_ISA_C67_BA, C67_SBASE_LO, 
			    (ISA_IDE_CNTRL_BA & 0xff));

	/* do the rest of the IDE1 registers */

	(void) C67_WRITE (CPU_ISA_C67_BA, C67_PIRQ_SEL, 
			    C67_IDE_INT_LVL); 			/* IRQ */
    
	/* enable the IDE1 registers */

	(void) C67_WRITE (CPU_ISA_C67_BA, C67_ACTIVATE, C67_LUN_ENABLE);

	/* initialize IDE2 */

	(void) C67_WRITE (CPU_ISA_C67_BA, C67_LUN_INDEX, C67_LUN_IDE2);

	/* initialize the IDE2 address */
    
	(void) C67_WRITE (CPU_ISA_C67_BA, C67_PBASE_HI, C67_DISABLE );
	(void) C67_WRITE (CPU_ISA_C67_BA, C67_PBASE_LO, C67_DISABLE );
	(void) C67_WRITE (CPU_ISA_C67_BA, C67_SBASE_HI, C67_DISABLE );
	(void) C67_WRITE (CPU_ISA_C67_BA, C67_SBASE_LO, C67_DISABLE );
    
	/* do the rest of the IDE2 registers */

	(void) C67_WRITE (CPU_ISA_C67_BA, C67_PIRQ_SEL, C67_DISABLE); /* IRQ */
	(void) C67_WRITE (CPU_ISA_C67_BA, C67_MODE_REG, C67_DISABLE); /* mode */
    
	/* enable the IDE2 registers */

	(void) C67_WRITE (CPU_ISA_C67_BA, C67_ACTIVATE, C67_LUN_DISABLE);

	/* initialize the RTC */

	(void) C67_WRITE (CPU_ISA_C67_BA, C67_LUN_INDEX, C67_LUN_RTC);

	/* do the rest of the RTC registers */

	(void) C67_WRITE (CPU_ISA_C67_BA, C67_PIRQ_SEL, C67_DISABLE); /* IRQ */
	(void) C67_WRITE (CPU_ISA_C67_BA, C67_MODE_REG, C67_DISABLE); /* mode */
	(void) C67_WRITE (CPU_ISA_C67_BA, C67_OPTS_REG, C67_DISABLE); /* opt */ 

	/* enable the RTC device */

	(void) C67_WRITE (CPU_ISA_C67_BA, C67_ACTIVATE, C67_LUN_ENABLE);
	}

    /* exit the configuration state */

    * (UINT8 *)(CPU_ISA_C67_BA) = CONFIG_EXIT;
    EIEIO_SYNC;
    }