w83c553f.c

仍然是MBX860中的通用配置文件源代码

/* w83c553f.c - Winbond Interrupt Controller Driver */

/* Copyright 1984-1998 Wind River Systems, Inc. */
/* Copyright 1997,1998 Motorola, Inc., All Rights Reserved */
#include "copyright_wrs.h"

/*
modification history
--------------------
01d,10jun98,dat  added sysLib.h, removed conflicting prototypes.
01c,08may98,map  removed sysVectorIRQ0, added IBC_INUM_* macros.
01b,17nov97,rhk  added Description, WRS code review changes
01a,11nov96,rhk  created by Motorola, from version 01h of sl82565IntrCtl.c.
*/

/*
DESCRIPTION

This module implements the Winbond W83C553 PCI-ISA Bridge (PIB) driver. The
W83C553 PIB was formerly known as the Motorola sl82565 ISA Bridge Controller
(IBC).

The W83C553 Chip is a highly integrated ASIC providing PCI-ISA interface
chip.  It provides following major capabilities:

  PCI Bus Master capability for ISA DMA.
  PCI Arbiter capability
  PCI Power management control
  64 byte PCI bus FIFO for burst capability
  Standard ISA interrupt controllers (82C59)
  Standard ISA timer/counter (82C54)

This driver is limited to the interrupt controller feature of the chip.
This driver does not interact with any other drivers supporting the
W83C553 chip.

The chip implements a standard ISA bus interrupt system consisting of
two 82C59A interrupt controller units.  The two units are cascaded
together to provide 15 actual interrupt lines.  The first unit implements
interrupt number 0 thru 7.  Interrupt number 2 is the cascaded input
from the second 82C59A controller, so it functionally does not exist
as a user input.  The inputs on the second controller are numbered 8 through
15.  Since they are cascaded into interrupt number 2 on the first unit,
their actual priority is higher than inputs 3 through 7 on the first
unit.  The true priority heirarchy (from high to low) is: 0, 1, 8, 9,
10, 11, 12, 13, 14, 15, 3, 4, 5, 6, 7.  The highest priority input that
is active is the unit that shall receive service first.

This driver implements a complete interrupt architecture system, complete
with vector table.

Based on the IBM-PC legacy system, this driver supports 16 levels, each
of which maps to a single vector.  Since PCI interrupt lines are shared, this
driver does provide for overloading of interrupt routines (i.e. there is
a list of interrupt routines for each interrupt vector (level)).  To service
a vector requires that all connected interrupt routines be called in order
of their connection.

This driver provides the vector table for the system.  It can support
a total of 256 vectors.  The interrupt controller device can only generate
16 different vectors though, one for each level.

The interrupt number corresponding to IRQ0 is determined by the macro
IBC_INUM_BASE. Other numbers are generated by adding the IRQ number to this
vector number. The interrupts are mapped to system interrupts by
adding IBC_INUM_SYS_BASE.

If there are other devices in the system capable of generating their own
vectors then we presume that an appropriate interrupt handler is created
and attached to the vector associated with the correct IRQ number.  That
interrupt handler would get a new vector directly from the device and then
call all of the handlers attached to that new vector.  Vector information is
stored in a linked list of INT_HANDLER_DESC structures. The sysIntTbl array
contains a pointer to the first entry for each vector.

INTERNAL
.SH INITIALIZATION

This driver is initialized from the BSP, usually as part of sysHwInit().
The first routine to be called is sysIbcPciExtInit(). The arguments
to this routine are the bus, device, and function numbers that locate
the chip in the PCI configuration space.  The routine verifies the type
of device and then initializes the interrupt pins routine to IRQ numbers.

The second routine to be called is sysIbcInit().  This routine takes no
arguments. This routine allocates the vector table and initializes the
chips to a default state.  All individual interrupt sources are disabled.
Each has to be individually enabled by intEnable() before it will be
unmasked and allowed to generate an interrupt.

Typical device initialization looks like this:

.CS
  /@ Initialize the extended portion of the IBC's PCI Header.  @/

  int pciBusNum;
  int pciDevNum;
  int pciFuncNum;

  if (pciFindDevice ((PCI_ID_W83C553F & 0xFFFF), 
		       (PCI_ID_W83C553F >> 16) & 0xFFFF, 0,
                       &pciBusNum, &pciDevNum, &pciFuncNum) != ERROR)
      {
      sysIbcPciExtInit (pciBusNum, pciDevNum, pciFuncNum);
      sysIbcInit ();
      }
.CE

.SH CUSTOMIZING THIS DRIVER

The macros IBC_BYTE_OUT and IBC_BYTE_IN provide the hardware access methods.
By default they call the routines sysOutByte() and sysInByte(), which are
presumed to be defined by the BSP.  The user may redefine these macros
as needed.

The macros CPU_INT_LOCK() and CPU_INT_UNLOCK provide the access
to the CPU level interrupt lock/unlock routines.  We presume that there
is a single interrupt line to the CPU.  By default these macros call
intLock() and intUnlock() respectively.
*/


/* includes */

#include "sysLib.h"
#include "w83c553f.h"

/* defines */

/* globals */

/* system interrupt table */

LOCAL	INT_HANDLER_DESC *   intVecTable[NUM_VEC_MAX];

#ifdef INCLUDE_INSTRUMENTATION
IMPORT	int             evtTimeStamp;
#endif

/* forward declarations */

LOCAL void	sysIbcEndOfInt (int);
LOCAL void	sysIbcIntLevelSet (int);
STATUS          sysIbcIntConnect (VOIDFUNCPTR *, VOIDFUNCPTR, int);
void            sysIbcIntEnable (int);
void            sysIbcIntDisable (int);
void            sysIbcIntHandler (void);


/* Mask values are the currently disabled sources */

LOCAL UINT8	sysPicMask1 = 0xfb;	/* all levels disabled */
LOCAL UINT8	sysPicMask2 = 0xff;

/* Level values are the interrupt level masks */

LOCAL UINT8	sysPicLevel1;
LOCAL UINT8	sysPicLevel2;
LOCAL UINT8	sysPicLevelCur;		/* current priority level, 0 to 16 */

/* level values by real priority */

LOCAL UCHAR sysPicPriMask1[17] = {0xFB,0xFA,0xF8,0xF8,0xF0,0xE0,0xC0,0x80,
			     0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0x0};
LOCAL UCHAR sysPicPriMask2[17] = {0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,
			     0xFF,0xFE,0xFC,0xF8,0xF0,0xE0,0xC0,0x80,0x0};


/* Hardware access methods */

#ifndef IBC_BYTE_OUT
#   define IBC_BYTE_OUT(reg,data) 	(sysOutByte (reg,data))
#endif

#ifndef IBC_BYTE_IN
#   define IBC_BYTE_IN(reg,pData) 	(*pData = sysInByte(reg))
#endif

#ifndef IBC_LONG_IN
#   define IBC_LONG_IN(reg,pData) 	(*pData = sysInLong(reg))
#endif


#ifndef CPU_INT_LOCK
#   define CPU_INT_LOCK(pData)		(*pData = intLock ()) 
#endif

#ifndef CPU_INT_UNLOCK
#   define CPU_INT_UNLOCK(data) 	(intUnlock (data))
#endif

/*******************************************************************************
*
* sysIbcPciExtInit - initialize the extended portion of the IBC PCI header
*
* This routine initializes the extended portion of the ISA Bridge Controller
* (IBC) PCI header.
*
* RETURNS: OK or ERROR.
*
* SEE ALSO: 
*/

STATUS sysIbcPciExtInit
    (
    int         pciBusNo,               /* PCI bus number */
    int         pciDevNo,               /* PCI device number */
    int         pciFuncNo               /* PCI function number */
    )
    {
    /*
     * route PCI interrupts to IBC IRQs
     *
     * PCI IRQ0 routed to IBC IRQ9	(PCI INTA)
     * PCI IRQ1 routed to IBC IRQ10	(PCI INTB)
     * PCI IRQ2 routed to IBC IRQ11	(PCI INTC)
     * PCI IRQ3 routed to IBC IRQ13	(PCI INTD)
     */

    pciConfigOutWord (pciBusNo, pciDevNo, pciFuncNo, PCI_CFG_IBC_INTR_ROUTE,
                      0x9abd);

    return (OK);
    }


/*******************************************************************************
*
* sysIbcInit - Initialize the IBC
*
* This routine initializes the non-PCI Header configuration registers of the
* IBC within the W83C553 PIB.
*
* RETURNS: OK always
*/

STATUS sysIbcInit (void)
    {
    UINT        vector;
    UCHAR	intVec;

    /* Initialize the interrupt table */

    for (vector = 0; vector < 256; vector++)
	intVecTable[vector] = NULL;

    /* Initialize the Interrupt Controller #1 */

    IBC_BYTE_OUT (PIC_port1 (PIC1_BASE_ADR), 0x11);		/* ICW1 */
    IBC_BYTE_OUT (PIC_port2 (PIC1_BASE_ADR), IBC_INUM_BASE);	/* ICW2 */
    IBC_BYTE_OUT (PIC_port2 (PIC1_BASE_ADR), 0x04);		/* ICW3 */
    IBC_BYTE_OUT (PIC_port2 (PIC1_BASE_ADR), 0x01);		/* ICW4 */

    /*
     *	Mask interrupts IRQ 0, 1, and 3-7 by writing to OCW1 register
     *	IRQ 2 is the cascade input
     */

    IBC_BYTE_OUT (PIC_IMASK (PIC1_BASE_ADR), 0xfb);

    /* Make IRQ 5 level sensitive */

    IBC_BYTE_OUT (W83C553F_INT1_ELC, 0x20);

    /* Initialize the Interrupt Controller #2 */

    IBC_BYTE_OUT (PIC_port1 (PIC2_BASE_ADR), 0x11);	/* ICW1 */
    IBC_BYTE_OUT (PIC_port2 (PIC2_BASE_ADR), IBC_INUM_BASE+8); /* ICW2 */
    IBC_BYTE_OUT (PIC_port2 (PIC2_BASE_ADR), 0x02);	/* ICW3 */
    IBC_BYTE_OUT (PIC_port2 (PIC2_BASE_ADR), 0x01);	/* ICW4 */

    /* Mask interrupts IRQ 8-15 by writing to OCW1 register */

    IBC_BYTE_OUT (PIC_IMASK (PIC2_BASE_ADR), 0xff);

    /* Make IRQ 15, 14, 11, 10, and 9 level sensitive */

    IBC_BYTE_OUT (W83C553F_INT2_ELC, 0x80 | 0x40 | 0x08 | 0x04 | 0x02);

    /* 
     * connect and enable the ISA interrupt handler.  This is installed into
     * the SIU Interrupt Controller, which functions as the main interrupt
     * controller for the MBX860. Use IRQ3 as the source in the SIU
     */