qspanpci.c

mbx860的BSP相关配置文件中的一个

/* qspanPci.c -  QSpan (QBus Controller) Initialization Module */

/* Copyright 1998 Wind River Systems, Inc. */
/* Copyright 1997,1998 Motorola, Inc., All Rights Reserved */

/*
modification history
--------------------
01h,31jul98,rhk  added check for revision number, enable normal 
		 termination of PCI Config. cycles for rev. 1.2 QSPAN chips.
01g,24mar98,rhk  changed macro names in qspanHostInit.
01f,12mar98,rhk  added 5 additional functions to the driver.
01e,04mar98,dat  rewrite for std names, documentation, standards.
01d,17nov97,rhk  changed register access to macros, added description
01c,25aug97,srr  replaced including of pci.h with drv/pci/pciIomapLib.h
01b,12may97,srr  modified for VxWorks.
01a,24oct96,rb   created.
*/

/*
DESCRIPTION
This module provides the necessary initialization for the QSPAN PCI
bus bridge device.  This device provides access to/from the Motorola
QBus (the processor bus) and the PCI bus.

Notes on the programming of the QSPAN:

.IP "1"
The QSPAN is setup to allow big-endian or little-endian access via the QBus.
The QSPAN provides the necessary lane translations.  Therefore, if big-endian
is selected, from the CPU point of view, all reads and writes to the
PCI use big-endian data.

.IP "2"
Of the two target images available, only target image 0 is enabled.
It is setup to respond to PCI memory accesses on the PCI bus, and will
translate these to DRAM acesses.  Write posting is enabled.  Target image 1
can be programmed by the user using the call: qspanTargetImageSet.
.CS
Default PCI to CPU Address Space Translation
PCI address range:	0x8000_0000 - 0xFFFF_FFFF to
CPU address range:	0x0000_0000 - 0x7FFF_FFFF
.CE

.IP "3"
The slave images (which allow access to the PCI bus from the CPU)
are setup as 512MB windows, image 0 for PCI I/O access, image 1 for 
PCI memory space access.

.CS
Default CPU to PCI Address Space Translation

-----------------------------------------------------------
CPU Space	PCI I/O Space	   Size		  Access to

0x80000000	0x00000000           8 MB         ISA I/O space
0x81000000	0x01000000         496 MB         PCI I/O space

		PCI MEM Space 	   Size		  Access to

0xc0000000	0x00000000           8 MB         ISA MEM space
0xc1000000	0x01000000         496 MB         PCI MEM space
.CE

.IP "4"
All QSPAN interrupts are mapped to the QBus, but are setup to
be disabled.


default definitions for read/write assume 32bit memory mapped accesses.
QSPAN_READ(addr,result)
QSPAN_WRITE(addr,value)

*/

/* includes */
#include "vxWorks.h"		/* types */
#include "qspanPci.h"		/* QSpan (PCI Bridge Controller) definitions */ 
#include "config.h"
#include "drv/pci/pciConfigLib.h"	/* To get PCI_BASE_IO macro */

/* globals */

int sysQspanRevisionId;

/* Macros for all i/o operations to use */

#define EIEIO_SYNC  __asm__("	eieio;	sync")

#ifndef QSPAN_READ
#define QSPAN_READ(readAddr, lvalue)	\
	(lvalue = *(UINT32 *)(readAddr))
#endif

#ifndef QSPAN_WRITE
#define QSPAN_WRITE(writeAddr, value)	\
	(*(UINT32 *)(writeAddr) = value)
#endif

/* forward declarations */

void qspanHostReset ( UINT32 );
void qspanHostEnable ( UINT32 );
void qspanTargetImageSet ( UINT32, UINT32, UINT32, UINT32, UINT32 );
void qspanSlaveImageSet ( UINT32, UINT32, UINT32, UINT32 );
STATUS qspanRegMap ( UINT32, UINT32, UINT32 );
void qspanHostInit ( UINT32 );

/******************************************************************************
*
* qspanHostInit - initialize the QSpan PCIBus bridge controller
*
* This function's purpose is to initialize the QSpan device.  This
* device spans the QBus to PCIBus.
*
* RETURNS: N/A
*/

void qspanHostInit
    (
    UINT32	qspanAdr	/* base address of the QSpan device regs. */
    )
    {

    /* get the revision number of the QSPAN chip first */

    QSPAN_READ(qspanAdr + QSPAN_PCI_CLASS, sysQspanRevisionId);
    sysQspanRevisionId = (sysQspanRevisionId & QSPAN_REV_ID_MASK);

    /*
     * clear all PCI error status
     * disable SERR, and PERR
     * disable I/O-space, memory-space, and bus mastering
     * (reset the QSPAN)
     */

    qspanHostReset(qspanAdr);

    /* disable all slave and target images */

    QSPAN_WRITE(qspanAdr + QSPAN_PBTI0_CTL, QSPAN_DISABLE_REG);
    QSPAN_WRITE(qspanAdr + QSPAN_PBTI1_CTL, QSPAN_DISABLE_REG);
    QSPAN_WRITE(qspanAdr + QSPAN_QBSI0_AT,  QSPAN_DISABLE_REG);
    QSPAN_WRITE(qspanAdr + QSPAN_QBSI1_AT,  QSPAN_DISABLE_REG);
    EIEIO_SYNC;

    /*
     * set latency timer to default value
     * disable cache line
     */

    QSPAN_WRITE(qspanAdr + QSPAN_PCI_MISC0,
		QSPAN_DEF_CACHELINE | QSPAN_DEF_LAT_TIMER );

    /*
     * allow PCI access to the 4KByte register file in PCI memory space
     * (put at bottom, the PCI autoconfigure routine places PCI-memory
     * devices found from the top of PCI memory space down)
     *
     */

    if (QSPAN_CTL_PCI_MEM == QSPAN_ENABLE_REG)
	(void)qspanRegMap(qspanAdr, QSPAN_PCI_MEM_SPACE, QSPAN_CFG_BA_MEM);

    /*
     * allow PCI access to the 4KByte register file in PCI I/O space
     * (put at top, the PCI autoconfigure routine places PCI-I/O
     * devices found from the bottom of PCI I/O space up)
     *
     */

    if (QSPAN_CTL_PCI_IO == QSPAN_ENABLE_REG)
	(void)qspanRegMap(qspanAdr, QSPAN_PCI_IO_SPACE, QSPAN_CFG_BA_IO);

    /* disable the PCI configuration expansion ROM */

    QSPAN_WRITE (qspanAdr + QSPAN_PCI_BSROM, QSPAN_DISABLE_REG);

    /* set interrupt line to zero */

    QSPAN_WRITE(qspanAdr + QSPAN_PCI_MISC1, QSPAN_DISABLE_REG);

    /*
     * setup the target image #0 and target image #1 address and
     * control registers ( primarily used to map PCI access to 
     * local memory )
     */

    qspanTargetImageSet(qspanAdr, QSPAN_TARGET_IMAGE_0,
			QSPAN_PBTI_BA_0, QSPAN_PBTI_TA_0,
			QSPAN_PBTI_CTL_REG0);

    qspanTargetImageSet(qspanAdr, QSPAN_TARGET_IMAGE_1,
                        QSPAN_PBTI_BA_1, QSPAN_PBTI_TA_1,
                        QSPAN_PBTI_CTL_REG1);


    /* enable error logging */

    QSPAN_WRITE(qspanAdr + QSPAN_PB_ERRCS, QSPAN_ENABLE_ERR_LOG);

    /*
     * clear all IDMA error status
     * initialize to PowerQUICC mode
     */

    QSPAN_WRITE(qspanAdr + QSPAN_IDMA_CS,
		QSPAN_CLR_IRST | QSPAN_CLR_DONE | QSPAN_CLR_IPE | 
		QSPAN_CLR_IQE | QSPAN_SET_IMODE );

    /*
     * clear all interrupt status
     * disable all interrupts
     * map all interrupts to the QBus
     */

    QSPAN_WRITE(qspanAdr + QSPAN_INT_STAT, 
		QSPAN_CLR_PEL_IS | QSPAN_CLR_QEL_IS | 
		QSPAN_CLR_DPD_IS | QSPAN_CLR_IPE_IS | 
		QSPAN_CLR_IQE_IS | QSPAN_CLR_IRST_IS |
		QSPAN_CLR_DONE_IS | QSPAN_CLR_SI1_IS | 
		QSPAN_CLR_SI0_IS );
    QSPAN_WRITE(qspanAdr + QSPAN_INT_CTL, QSPAN_DISABLE_REG);
    QSPAN_WRITE(qspanAdr + QSPAN_INT_DIR, QSPAN_DISABLE_REG);

    /*
     * setup the synchronous bus grant and bus grant acknowledge,
     * setup the byte ordering: big endian or little endian
     * setup the master/slave mode
     * for QSPAN chips of rev. 1.2 or greater, set the Master Abort
     * bit to disable Bus error mapping
     */

    if (sysQspanRevisionId < QSPAN_REVISION_1_2)
        QSPAN_WRITE(qspanAdr + QSPAN_MISC_CTL, 
		    QSPAN_DEF_BUS_GRANT | QSPAN_DEF_BG_ACK |
		    QSPAN_DEF_BYTE_ORDER | QSPAN_DEF_MSTSLV_MODE );
    else
	QSPAN_WRITE(qspanAdr + QSPAN_MISC_CTL,
		    QSPAN_DEF_BUS_GRANT | QSPAN_DEF_BG_ACK |
		    QSPAN_DEF_BYTE_ORDER | QSPAN_MA_BE_D |
		    QSPAN_DEF_MSTSLV_MODE );

    /* setup the QSPAN slave image #0 to default values */

    qspanSlaveImageSet(qspanAdr, QSPAN_SLAVE_IMAGE_0,
		       QSPAN_QBSI_CTL_REG0, QSPAN_QBSI_AT_REG0);

    /* setup the QSPAN slave image #0 to default values */

    qspanSlaveImageSet(qspanAdr, QSPAN_SLAVE_IMAGE_1,
		       QSPAN_QBSI_CTL_REG1, QSPAN_QBSI_AT_REG1);

    /* clear all QBus error status */

    QSPAN_WRITE(qspanAdr + QSPAN_QB_ERRCS, QSPAN_CLR_QES);
    EIEIO_SYNC;
    }

/******************************************************************************
*
* qspanRegMap - map QSPAN registers
*
* This function will map a 4KB block in either PCI memory of I/O space
* to allow access to the QSPAN register set.
*
*
* RETURNS: N/A
*/

STATUS qspanRegMap
    (
    UINT32      qspanAdr,        /* base address of the QSpan device regs. */
    UINT32      pciSpace,
    UINT32      baseAdr
    )
    {
    if ( (pciSpace != QSPAN_PCI_MEM_SPACE) || (pciSpace != QSPAN_PCI_IO_SPACE))
	return(ERROR);

    if ( pciSpace == QSPAN_PCI_MEM_SPACE)

	/* allow PCI access to the 4KByte register file in PCI memory space */

	QSPAN_WRITE(qspanAdr + QSPAN_PCI_BSM, baseAdr);

    else

	/* allow PCI access to the 4KByte register file in PCI I/O space */

	QSPAN_WRITE(qspanAdr + QSPAN_PCI_BSIO, (baseAdr | pciSpace));
    return(OK);
    }

/******************************************************************************
*
* qspanSlaveImageSet - setup a PCI slave image
*
* This function will program one of the QSPAN PCI slave images
* (CPU to PCI mapping).
*
* RETURNS: N/A
*/

void qspanSlaveImageSet
    (
    UINT32      qspanAdr,       /* base address of the QSpan device regs. */
    UINT32      image,          /* slave image number 0 or 1 */
    UINT32      cntrlRegValue,  /* value to be stored in the slave image */
                                /* control register */
    UINT32	adrRegValue	/* value to be stored in the slave image */
				/* address translation register */
    )
    {
    if (image == QSPAN_SLAVE_IMAGE_0)
        {

        /* setup the slave image 0 control register */

        QSPAN_WRITE(qspanAdr + QSPAN_QBSI0_CTL, cntrlRegValue);

        /* setup the slave image 0 address register */

        QSPAN_WRITE(qspanAdr + QSPAN_QBSI0_AT, adrRegValue);
        }
    else
        {

        /* setup the slave image 1 control register */

        QSPAN_WRITE(qspanAdr + QSPAN_QBSI1_CTL, cntrlRegValue);

        /* setup the slave image 1 address register */

        QSPAN_WRITE(qspanAdr + QSPAN_QBSI1_AT, adrRegValue);
        }

    EIEIO_SYNC;
    }

/******************************************************************************
*
* qspanTargetImageSet - setup a PCI target image
*
* This function will program the selected QSPAN PCI target image
* (mapping the address space from the point of view of the PCI bus).
* It is used mostly for mapping access from PCI memory space to the
* local DRAM.
*
* RETURNS: N/A
*/

void qspanTargetImageSet
    (
    UINT32      qspanAdr,       /* base address of the QSpan device regs. */
    UINT32      image,          /* target image number 0 or 1 */
    UINT32      pciBaseAdr,     /* base address of the target image */
    UINT32      translateAdr,   /* base address for translation of target adr */
    UINT32	cntrlRegValue   /* value to be stored in the target image */
				/* control register */
    )
    {

    if (image == QSPAN_TARGET_IMAGE_0)
        {

        /* setup the target image 0 address register */

        QSPAN_WRITE(qspanAdr + QSPAN_PBTI0_ADD, ((pciBaseAdr & 0xffff0000) |
                                                 (translateAdr >> 16 )) );

	/* setupt the target image 0 control register */

	QSPAN_WRITE(qspanAdr + QSPAN_PBTI0_CTL, cntrlRegValue);
	}
    else
        {

        /* setup the target image 1 address register */

        QSPAN_WRITE(qspanAdr + QSPAN_PBTI1_ADD, ((pciBaseAdr & 0xffff0000) |
                                                 (translateAdr >> 16 )) );

        /* setupt the target image 0 control register */

        QSPAN_WRITE(qspanAdr + QSPAN_PBTI1_CTL, cntrlRegValue);
        }

    EIEIO_SYNC;
    }

/******************************************************************************
*
* qspanHostEnable - enable the bridge
*
* This function enables I/O-space, memory-space, and bus mastering on
* the host.
*
* RETURNS: N/A
*/

void qspanHostEnable
    (
    UINT32      qspanAdr        /* base address of the QSpan device regs. */
    )
    {
    UINT32 temp;

    /*
     * clear all QBus error status
     * enable QBus error log
     */

    QSPAN_WRITE(qspanAdr + QSPAN_QB_ERRCS,
                QSPAN_ENABLE_ERR_LOG | QSPAN_CLR_QES);

    /* enable I/O-space, memory-space, and bus mastering */

    EIEIO_SYNC;
    QSPAN_READ (qspanAdr + QSPAN_PCI_CS, temp);
    QSPAN_WRITE (qspanAdr + QSPAN_PCI_CS,
                temp | QSPAN_ENABLE_BM | QSPAN_ENABLE_MS |
                QSPAN_ENABLE_IOS);
    EIEIO_SYNC;
    }

/******************************************************************************
*
* qspanHostReset - reset the QSpan PCIBus bridge controller
*
* This function's purpose is to reset the QSpan device.
*
* RETURNS: N/A
*/
void qspanHostReset
    (
    UINT32      qspanAdr        /* base address of the QSpan device regs. */
    )
    {

    /*
     * clear all PCI error status
     * disable SERR, and PERR
     * disable I/O-space, memory-space, and bus mastering
     */

    QSPAN_WRITE(qspanAdr + QSPAN_PCI_CS,
                QSPAN_CLR_D_PE | QSPAN_CLR_S_SERR | QSPAN_CLR_R_MA |
                QSPAN_CLR_R_TA | QSPAN_CLR_S_TA | QSPAN_CLR_DP_D);
    EIEIO_SYNC;

    }