p2s.map.qmsg

本程序是关于SDI 接口的描述

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 08 14:39:43 2006 " "Info: Processing started: Fri Sep 08 14:39:43 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off p2s -c p2s " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off p2s -c p2s" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "p2s.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file p2s.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 p2s-a_all " "Info: Found design unit 1: p2s-a_all" {  } { { "p2s.vhd" "" { Text "E:/work_document/ASI_Embed_FPGA(20060908)/ASI_Source_Program(20060908)/asi&sdi/auk_sdsdi-v1.1/source_vhdl/sdi_transmit/p2s.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 p2s " "Info: Found entity 1: p2s" {  } { { "p2s.vhd" "" { Text "E:/work_document/ASI_Embed_FPGA(20060908)/ASI_Source_Program(20060908)/asi&sdi/auk_sdsdi-v1.1/source_vhdl/sdi_transmit/p2s.vhd" 40 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_IS_NOT_COMPILED_IN_LIBRARY" "sdi_std_logic work p2s.vhd(38) " "Error (10481): VHDL Use Clause error at p2s.vhd(38): design library \"work\" does not contain primary unit \"sdi_std_logic\"" {  } { { "p2s.vhd" "" { Text "E:/work_document/ASI_Embed_FPGA(20060908)/ASI_Source_Program(20060908)/asi&sdi/auk_sdsdi-v1.1/source_vhdl/sdi_transmit/p2s.vhd" 38 0 0 } }  } 0 10481 "VHDL Use Clause error at %3!s!: design library \"%2!s!\" does not contain primary unit \"%1!s!\"" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Fri Sep 08 14:39:45 2006 " "Error: Processing ended: Fri Sep 08 14:39:45 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}