📄 conf_tny.lst
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A51 MACRO ASSEMBLER CONF_TNY 12/27/2008 15:34:43 PAGE 1
MACRO ASSEMBLER A51 V8.01
OBJECT MODULE PLACED IN CONF_TNY.OBJ
ASSEMBLER INVOKED BY: e:\Keil\C51\BIN\A51.EXE CONF_TNY.A51 SET(LARGE) DEBUG EP
LOC OBJ LINE SOURCE
1 $nomod51
2 ;------------------------------------------------------------------------------
3 ; This file is part of the RTX-51 TINY Real-Time Operating System Package
4 ; Copyright KEIL ELEKTRONIK GmbH and Keil Software, Inc. 1991-2002
5 ; Version 2.01
6 ;------------------------------------------------------------------------------
7 ; CONF_TNY.A51: This code allows the configuration of the
8 ; RTX-51 TINY Real-Time Operating System
9 ;
10 ; Copy this file to your project folder and add the copy to your uVision2
11 ; project. You can customize several parameters of RTX51 Tiny within this
12 ; configuration file.
13 ;
14 ; If you use command line tools, translate this file with:
15 ;
16 ; Ax51 CONF_TNY.A51
17 ;
18 ; If you use command line tools, link the modified CONF_TNY.OBJ file to
19 ; your application with:
20 ;
21 ; Lx51 <your object file list>, CONF_TNY.OBJ <controls>
22 ;
23 ;------------------------------------------------------------------------------
24 ;
25 ; RTX-51 TINY Hardware-Timer
26 ; ==========================
27 ;
28 ; With the following EQU statements the initialization of the RTX-51 TINY
29 ; Hardware-Timer can be defined (RTX-51 TINY uses the 8051 Timer 0 for
30 ; controlling RTX-51 software timers).
31 ;
32 ; Define the register bank used for the timer interrupt.
0001 33 INT_REGBANK EQU 1 ; default is Registerbank 1
34 ;
35
36
37
38
39
40
41
42
43
44
45 ; Define Hardware-Timer tick time in 8051 machine cycles.
46
47
0BFA 48 INT_CLOCK EQU 3066
49
50
51 ;
52 ; Define Round-Robin Timeout in Hardware-Timer ticks.
0005 53 TIMESHARING EQU 5 ; default is 5 Hardware-Timer ticks.
54 ; ; 0 disables Round-Robin Task Switching
55 ;
56 ; Long User Interrupt Routines: set to 1 if your application contains
57 ; user interrupt functions that may take longer than a hardware timer
58 ; interval for execution.
A51 MACRO ASSEMBLER CONF_TNY 12/27/2008 15:34:43 PAGE 2
0000 59 LONG_USR_INTR EQU 0 ; 0 user interrupts execute fast.
60 ; ; 1 user interrupts take long execution times.
61 ;
62 ;
63 ;------------------------------------------------------------------------------
64 ;
65 ; USER CODE FOR 8051 HARDWARE TIMER INTERRUPT
66 ; ===========================================
67 ;
68 ; The following macro defines the code executed on a hardware timer interrupt.
69 ;
70 ; Define instructions executed on a hardware timer interrupt.
71 HW_TIMER_CODE MACRO
72 ; Empty Macro by default
73 RETI
74 ENDM
75 ;
76 ;
77 ;------------------------------------------------------------------------------
78 ;
79 ; CODE BANKING SUPPORT
80 ; ====================
81 ;
82 ; The following EQU statement controls the code banking support for RTX51 TINY.
83 ;
84 ; Enable or disable code banking support
0000 85 CODE_BANKING EQU 0 ; 0 (default) application uses no code banking
86 ; ; 1 application uses code banking
87 ;
88 ;------------------------------------------------------------------------------
89 ;
90 ; RTX-51 TINY Stack Space
91 ; =======================
92 ;
93 ; The following EQU statements defines the size of the internal RAM used
94 ; for stack area and the minimum free space on the stack. A macro defines
95 ; the code executed when there is there is not enough free stack on the
96 ; CPU stack.
97 ;
98 ; Define the highest RAM address used for CPU stack
00FF 99 RAMTOP EQU 0FFH ; default is address (256-1)
100 ;
0014 101 FREE_STACK EQU 20 ; default is 20 bytes free space on stack
102 ; ; the value 0 disables stack checking
103 ;
104 STACK_ERROR MACRO
105 CLR EA ; disable interrupts
106 SJMP $ ; endless loop if stack space is exhausted
107 ENDM
108 ;
109 ;
110 ;------------------------------------------------------------------------------
111 ;
112 ; 8051 CPU IDLE CODE
113 ; ==================
114 ;
115 ; Many 8051 devices provide an IDLE MODE that reduces power consumption and
116 ; EMC. The following macro defines the code executed when there is no
117 ; ready task in the system. The code must set the CPU into an IDLE MODE
118 ; that stops instruction execution until an 8051 hardware interrupt occurs.
119 ;
120
121 ; Disable or Enable CPU_IDLE CODE
0001 122 CPU_IDLE_CODE EQU 1 ; 0 CPU_IDLE MACRO is not inserted
123 ; 1 CPU_IDLE MACRO is executed
124
A51 MACRO ASSEMBLER CONF_TNY 12/27/2008 15:34:43 PAGE 3
0087 125 PCON DATA 087H ; Power Control SFR on most 8051 devices
126
127 ; Stop CPU execution until hardware interrupt; executed when there is no
128 ; active task in the system.
129 CPU_IDLE MACRO
130 ORL PCON,#1 ; set 8051 CPU to IDLE
131 ENDM
132 ;
133 ;
134 ;------------------------------------------------------------------------------
135 ;----------------- !!! End of User Configuration Part !!! ------------------
136 ;----------------- !!! Do not modify code sections below !!! ------------------
137 ;------------------------------------------------------------------------------
138
139 ; SFR Symbols
00D0 140 PSW DATA 0D0H
00E0 141 ACC DATA 0E0H
00F0 142 B DATA 0F0H
0081 143 SP DATA 81H
0082 144 DPL DATA 82H
0083 145 DPH DATA 83H
0088 146 TCON DATA 88H
0089 147 TMOD DATA 89H
008A 148 TL0 DATA 8AH
008B 149 TL1 DATA 8BH
008C 150 TH0 DATA 8CH
008D 151 TH1 DATA 8DH
00A8 152 IE DATA 0A8H
153
154 ; TCON
008F 155 TF1 BIT 8FH
008E 156 TR1 BIT 8EH
008D 157 TF0 BIT 8DH
008C 158 TR0 BIT 8CH
008B 159 IE1 BIT 8BH
008A 160 IT1 BIT 8AH
0089 161 IE0 BIT 89H
0088 162 IT0 BIT 88H
163 ; IE
00AF 164 EA BIT 0AFH
00AC 165 ES BIT 0ACH
00AB 166 ET1 BIT 0ABH
00AA 167 EX1 BIT 0AAH
00A9 168 ET0 BIT 0A9H
00A8 169 EX0 BIT 0A8H
170
171 ; Check Configuration Values
172
173
174 NAME ?RTX51_TINY_KERNAL
175
176 PUBLIC ?RTX_CURRENTTASK
177 PUBLIC ?RTX_RAMTOP
178 PUBLIC os_switch_task
179 PUBLIC ?RTX?SET_ISR
180
181 EXTRN NUMBER (?RTX_MAXTASKN) ; max Task Number
182
00FF 183 ?RTX_RAMTOP EQU RAMTOP
F406 184 ?RTX_CLOCK EQU -INT_CLOCK
185
0008 186 ?RTX_REGISTERBANK EQU INT_REGBANK * 8
---- 187 DSEG AT ?RTX_REGISTERBANK
0008 188 DS 2 ; temporary space
000A 189 ?RTX_SAVEACC: DS 1
REG 190 saveacc EQU R2 ; for access in interrupt service routine
A51 MACRO ASSEMBLER CONF_TNY 12/27/2008 15:34:43 PAGE 4
000B 191 ?RTX_SAVEPSW: DS 1
REG 192 savepsw EQU R3 ; for access in interrupt service routine
000C 193 ?RTX_CURRENTTASK: DS 1
REG 194 currenttask EQU R4 ; for access in interrupt service routine
195
196 IF (TIMESHARING <> 0)
000D 197 ?RTX_ROBINTIME: DS 1
REG 198 robintime EQU R5 ; for access in interrupt service routine
199 ENDIF
200
201 IF (CODE_BANKING <> 0)
EXTRN DATA (?B_CURRENTBANK)
EXTRN CODE (?B_RESTORE_BANK)
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