📄 hal_nrf_l01.lst
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C51 COMPILER V8.08 HAL_NRF_L01 01/02/2009 11:50:57 PAGE 6
301 1 }
302
303 bool hal_nrf_tx_fifo_empty(void)
304 {
305 1 return (bool)((hal_nrf_read_reg(FIFO_STATUS) >> TX_EMPTY) & 1);
306 1 }
307
308 bool hal_nrf_tx_fifo_full(void)
309 {
310 1 return (bool)((hal_nrf_read_reg(FIFO_STATUS) >> TX_FIFO_FULL) & 1);
311 1 }
312
313 uint8_t hal_nrf_get_tx_fifo_status(void)
314 {
315 1 return ((hal_nrf_read_reg(FIFO_STATUS) & ((1<<TX_FIFO_FULL)|(1<<TX_EMPTY))) >> 4);
316 1 }
317
318 uint8_t hal_nrf_get_rx_fifo_status(void)
319 {
320 1 return (hal_nrf_read_reg(FIFO_STATUS) & ((1<<RX_FULL)|(1<<RX_EMPTY)));
321 1 }
322
323 uint8_t hal_nrf_get_fifo_status(void)
324 {
325 1 return hal_nrf_read_reg(FIFO_STATUS);
326 1 }
327
328 uint8_t hal_nrf_get_transmit_attempts(void)
329 {
330 1 return hal_nrf_read_reg(OBSERVE_TX) & (BIT_3|BIT_2|BIT_1|BIT_0);
331 1 }
332
333 bool hal_nrf_get_carrier_detect(void)
334 {
335 1 return hal_nrf_read_reg(CD) & 1;
336 1 }
337
338 void hal_nrf_write_tx_pload(uint8_t *tx_pload, uint8_t length)
339 {
340 1 hal_nrf_write_multibyte_reg(UINT8(HAL_NRF_TX_PLOAD), tx_pload, length);
341 1 }
342
343 void hal_nrf_setup_dyn_pl(uint8_t setup)
344 {
345 1 hal_nrf_write_reg(DYNPD, setup & ~0xC0);
346 1 }
347
348 void hal_nrf_enable_dynamic_pl(void)
349 {
350 1 hal_nrf_write_reg(FEATURE, (hal_nrf_read_reg(FEATURE) | 0x04));
351 1 }
352
353 void hal_nrf_disable_dynamic_pl(void)
354 {
355 1 hal_nrf_write_reg(FEATURE, (hal_nrf_read_reg(FEATURE) & ~0x04));
356 1 }
357
358 void hal_nrf_enable_ack_pl(void)
359 {
360 1 hal_nrf_write_reg(FEATURE, (hal_nrf_read_reg(FEATURE) | 0x02));
361 1 }
362
C51 COMPILER V8.08 HAL_NRF_L01 01/02/2009 11:50:57 PAGE 7
363 void hal_nrf_disable_ack_pl(void)
364 {
365 1 hal_nrf_write_reg(FEATURE, (hal_nrf_read_reg(FEATURE) & ~0x02));
366 1 }
367
368 void hal_nrf_enable_dynamic_ack(void)
369 {
370 1 hal_nrf_write_reg(FEATURE, (hal_nrf_read_reg(FEATURE) | 0x01));
371 1 }
372
373 void hal_nrf_disable_dynamic_ack(void)
374 {
375 1 hal_nrf_write_reg(FEATURE, (hal_nrf_read_reg(FEATURE) & ~0x01));
376 1 }
377
378 void hal_nrf_write_ack_pload(uint8_t pipe, uint8_t *tx_pload, uint8_t length)
379 {
380 1 CSN_LOW();
381 1
382 1 hal_nrf_rw(WR_ACK_PLOAD | pipe);
383 1 while(length--)
384 1 {
385 2 hal_nrf_rw(*tx_pload++);
386 2 }
387 1
388 1 CSN_HIGH();
389 1 }
390
391 uint8_t hal_nrf_read_rx_pl_w()
392 {
393 1 uint8_t temp;
394 1
395 1 CSN_LOW();
396 1
397 1 hal_nrf_rw(RD_RX_PLOAD_W);
398 1 temp = hal_nrf_rw(0);
399 1 CSN_HIGH();
400 1
401 1 return temp;
402 1 }
403
404 void hal_nrf_lock_unlock()
405 {
406 1 CSN_LOW();
407 1
408 1 hal_nrf_rw(LOCK_UNLOCK);
409 1 hal_nrf_rw(0x73);
410 1
411 1 CSN_HIGH();
412 1 }
413
414 uint8_t hal_nrf_get_rx_data_source(void)
415 {
416 1 return ((hal_nrf_nop() & (BIT_3|BIT_2|BIT_1)) >> 1);
417 1 }
418
419 // Fixed: returns length==0 and pipe==7 means FIFO empty
420
421 uint16_t hal_nrf_read_rx_pload(uint8_t *rx_pload)
422 {
423 1 return hal_nrf_read_multibyte_reg(UINT8(HAL_NRF_RX_PLOAD), rx_pload);
424 1 }
C51 COMPILER V8.08 HAL_NRF_L01 01/02/2009 11:50:57 PAGE 8
425
426 void hal_nrf_reuse_tx(void)
427 {
428 1 hal_nrf_write_reg(REUSE_TX_PL, 0);
429 1 }
430
431 bool hal_nrf_get_reuse_tx_status(void)
432 {
433 1 return (bool)((hal_nrf_get_fifo_status() & (1<<TX_REUSE)) >> TX_REUSE);
434 1 }
435
436 void hal_nrf_flush_rx(void)
437 {
438 1 hal_nrf_write_reg(FLUSH_RX, 0);
439 1 }
440
441 void hal_nrf_flush_tx(void)
442 {
443 1 hal_nrf_write_reg(FLUSH_TX, 0);
444 1 }
445
446 uint8_t hal_nrf_nop(void)
447 {
448 1 return hal_nrf_write_reg(NOP,0);
449 1 }
450
451 void hal_nrf_set_pll_mode(hal_nrf_pll_mode_t pll_mode)
452 {
453 1 if(pll_mode == HAL_NRF_PLL_LOCK)
454 1 {
455 2 hal_nrf_write_reg(RF_SETUP, (hal_nrf_read_reg(RF_SETUP) | (1<<PLL_LOCK)));
456 2 }
457 1 else
458 1 {
459 2 hal_nrf_write_reg(RF_SETUP, (hal_nrf_read_reg(RF_SETUP) & ~(1<<PLL_LOCK)));
460 2 }
461 1 }
462
463 hal_nrf_pll_mode_t hal_nrf_get_pll_mode(void)
464 {
465 1 return (hal_nrf_pll_mode_t)((hal_nrf_read_reg(RF_SETUP) & (1<<PLL_LOCK)) >> PLL_LOCK);
466 1 }
467
468 void hal_nrf_set_lna_gain(hal_nrf_lna_mode_t lna_gain)
469 {
470 1 if(lna_gain == HAL_NRF_LNA_HCURR)
471 1 {
472 2 hal_nrf_write_reg(RF_SETUP, (hal_nrf_read_reg(RF_SETUP) | (1<<LNA_HCURR)));
473 2 }
474 1 else
475 1 {
476 2 hal_nrf_write_reg(RF_SETUP, (hal_nrf_read_reg(RF_SETUP) & ~(1<<LNA_HCURR)));
477 2 }
478 1 }
479
480 hal_nrf_lna_mode_t hal_nrf_get_lna_gain(void)
481 {
482 1 return (hal_nrf_lna_mode_t) ( (hal_nrf_read_reg(RF_SETUP) & (1<<LNA_HCURR)) >> LNA_HCURR );
483 1 }
484
485 uint8_t hal_nrf_read_reg(uint8_t reg)
486 {
C51 COMPILER V8.08 HAL_NRF_L01 01/02/2009 11:50:57 PAGE 9
487 1 uint8_t temp;
488 1 CSN_LOW();
489 1 hal_nrf_rw(reg);
490 1 temp = hal_nrf_rw(0);
491 1 CSN_HIGH();
492 1
493 1 return temp;
494 1 }
495
496 uint8_t hal_nrf_write_reg(uint8_t reg, uint8_t value)
497 {
498 1 uint8_t retval;
499 1 CSN_LOW();
500 1 if(reg < WRITE_REG) // i.e. this is a register access
501 1 {
502 2 retval = hal_nrf_rw(WRITE_REG + reg);
503 2 hal_nrf_rw(value);
504 2 }
505 1 else // single byte cmd OR future command/register access
506 1 {
507 2 if(!(reg == FLUSH_TX) && !(reg == FLUSH_RX) && !(reg == REUSE_TX_PL) && !(reg == NOP))
508 2 {
509 3 retval = hal_nrf_rw(reg);
510 3 hal_nrf_rw(value);
511 3 }
512 2 else // single byte L01 command
513 2 {
514 3 retval = hal_nrf_rw(reg);
515 3 }
516 2 }
517 1 CSN_HIGH();
518 1
519 1 return retval;
520 1 }
521
522 uint16_t hal_nrf_read_multibyte_reg(uint8_t reg, uint8_t *pbuf)
523 {
524 1 uint8_t ctr, length;
525 1 switch(reg)
526 1 {
527 2 case HAL_NRF_PIPE0:
528 2 case HAL_NRF_PIPE1:
529 2 case HAL_NRF_TX:
530 2 length = ctr = hal_nrf_get_address_width();
531 2 CSN_LOW();
532 2 hal_nrf_rw(RX_ADDR_P0 + reg);
533 2 break;
534 2
535 2 case HAL_NRF_RX_PLOAD:
536 2 if( (reg = hal_nrf_get_rx_data_source()) < 7)
537 2 {
538 3 length = ctr = hal_nrf_read_rx_pl_w();
539 3
540 3 CSN_LOW();
541 3 hal_nrf_rw(RD_RX_PLOAD);
542 3 }
543 2 else
544 2 {
545 3 ctr = length = 0;
546 3 }
547 2 break;
548 2
C51 COMPILER V8.08 HAL_NRF_L01 01/02/2009 11:50:57 PAGE 10
549 2 default:
550 2 ctr = length = 0;
551 2 break;
552 2 }
553 1
554 1 while(ctr--)
555 1 {
556 2 *pbuf++ = hal_nrf_rw(0);
557 2 }
558 1
559 1 CSN_HIGH();
560 1
561 1 return (((uint16_t) reg << 8) | length);
562 1 }
563
564 void hal_nrf_write_multibyte_reg(uint8_t reg, uint8_t *pbuf, uint8_t length)
565 {
566 1 switch(reg)
567 1 {
568 2 case HAL_NRF_PIPE0:
569 2 case HAL_NRF_PIPE1:
570 2 case HAL_NRF_TX:
571 2 length = hal_nrf_get_address_width();
572 2 CSN_LOW();
573 2 hal_nrf_rw(WRITE_REG + RX_ADDR_P0 + reg);
574 2 break;
575 2
576 2 case HAL_NRF_TX_PLOAD:
577 2 CSN_LOW();
578 2 hal_nrf_rw(WR_TX_PLOAD);
579 2 break;
580 2 default:
581 2 break;
582 2 }
583 1
584 1 while(length--)
585 1 {
586 2 hal_nrf_rw(*pbuf++);
587 2 }
588 1
589 1 CSN_HIGH();
590 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 1569 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- 36
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
EDATA SIZE = ---- ----
HDATA SIZE = ---- ----
XDATA CONST SIZE = ---- ----
FAR CONST SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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