rc522reg.h

MFRC522 单片机读写程序

                                     \n <em><strong>Remark:</strong> This command can
                                     be activated by software, but only by a Power-On
                                     or Hard Reset </em>*/
/*@}*/


/* /////////////////////////////////////////////////////////////////////////////
 * Bit Definitions
 * ////////////////////////////////////////////////////////////////////////// */
/*! \name RC522 Bit definitions of Page 0
 *  \ingroup reg
 *  Below there are useful bit definition of the RC522 register set of Page 0.
 */
/*@{*/
/* Command Register							(01) */
#define     JBIT_RCVOFF             0x20   /*!< Switches the receiver on/off. */
#define     JBIT_POWERDOWN          0x10   /*!< Switches RC522 to Power Down mode. */

/* CommIEn Register							(02) */
#define     JBIT_IRQINV             0x80   /*!< Inverts the output of IRQ Pin. */

/* DivIEn Register							(03) */
#define     JBIT_IRQPUSHPULL        0x80   /*!< Sets the IRQ pin to Push Pull mode. */

/* CommIEn and CommIrq Register         (02, 04) */
#define     JBIT_TXI                0x40   /*!< Bit position for Transmit Interrupt Enable/Request. */
#define     JBIT_RXI                0x20   /*!< Bit position for Receive Interrupt Enable/Request. */
#define     JBIT_IDLEI              0x10   /*!< Bit position for Idle Interrupt Enable/Request. */
#define     JBIT_HIALERTI           0x08   /*!< Bit position for HiAlert Interrupt Enable/Request. */
#define     JBIT_LOALERTI           0x04   /*!< Bit position for LoAlert Interrupt Enable/Request. */
#define     JBIT_ERRI               0x02   /*!< Bit position for Error Interrupt Enable/Request. */
#define     JBIT_TIMERI             0x01   /*!< Bit position for Timer Interrupt Enable/Request. */

/* DivIEn and DivIrq Register           (03, 05) */
#define     JBIT_SIGINACTI          0x10   /*!< Bit position for SiginAct Interrupt Enable/Request. */
#define     JBIT_CRCI               0x04   /*!< Bit position for CRC Interrupt Enable/Request. */

/* CommIrq and DivIrq Register          (04, 05) */
#define     JBIT_SET                0x80   /*!< Bit position to set/clear dedicated IRQ bits. */

/* Error Register 							(06) */
#define     JBIT_WRERR              0x80   /*!< Bit position for Write Access Error. */
#define     JBIT_TEMPERR            0x40   /*!< Bit position for Temerature Error. */
#define     JBIT_BUFFEROVFL         0x10   /*!< Bit position for Buffer Overflow Error. */
#define     JBIT_COLLERR            0x08   /*!< Bit position for Collision Error. */
#define     JBIT_CRCERR             0x04   /*!< Bit position for CRC Error. */
#define     JBIT_PARITYERR          0x02   /*!< Bit position for Parity Error. */
#define     JBIT_PROTERR            0x01   /*!< Bit position for Protocol Error. */

/* Status 1 Register 						(07) */
#define     JBIT_CRCOK              0x40   /*!< Bit position for status CRC OK. */
#define     JBIT_CRCREADY           0x20   /*!< Bit position for status CRC Ready. */
#define     JBIT_IRQ                0x10   /*!< Bit position for status IRQ is active. */
#define     JBIT_TRUNNUNG           0x08   /*!< Bit position for status Timer is running. */
#define     JBIT_HIALERT            0x02   /*!< Bit position for status HiAlert. */
#define     JBIT_LOALERT            0x01   /*!< Bit position for status LoAlert. */

/* Status 2 Register				    		(08) */
#define     JBIT_TEMPSENSOFF        0x80   /*!< Bit position to switch Temperture sensors on/off. */
#define     JBIT_I2CFORCEHS         0x40   /*!< Bit position to forece High speed mode for I2C Interface. */
#define 	JBIT_TARGETACTIVATED	0x10
#define     JBIT_CRYPTO1ON          0x08   /*!< Bit position for reader status Crypto is on. */

/* FIFOLevel Register				    		(0A) */
#define     JBIT_FLUSHBUFFER        0x80   /*!< Clears FIFO buffer if set to 1 */

/* Control Register					    		(0C) */
#define     JBIT_TSTOPNOW           0x80   /*!< Stops timer if set to 1. */
#define     JBIT_TSTARTNOW          0x40   /*!< Starts timer if set to 1. */
#define		JBIT_WRNFCIDTOFIFO		0x20
#define		JBIT_INITIATOR			0X10

/* BitFraming Register					    (0D) */
#define     JBIT_STARTSEND          0x80   /*!< Starts transmission in transceive command if set to 1. */

/* BitFraming Register					    (0E) */
#define     JBIT_VALUESAFTERCOLL    0x80   /*!< Activates mode to keep data after collision. */
/*@}*/

/*! \name RC522 Bit definitions of Page 1
 *  \ingroup reg
 *  Below there are useful bit definition of the RC522 register set of Page 1.
 */
/*@{*/
/* Mode Register							(11) */
#define     JBIT_TXWAITRF           0x20   /*!< Tx waits until Rf is enabled until transmit is startet, else
                                                transmit is started immideately. */
#define     JBIT_POLSIGIN           0x08   /*!< Inverts polarity of SiginActIrq, if bit is set to 1 IRQ occures
                                                when Sigin line is 0. */

/* TxMode Register							(12) */
#define     JBIT_INVMOD             0x08   /*!< Activates inverted transmission mode. */

/* RxMode Register							(13) */
#define     JBIT_RXNOERR            0x08   /*!< If 1, receiver does not receive less than 4 bits. */

/* Definitions for Tx and Rx		    (12, 13) */
#define     JBIT_106KBPS            0x00   /*!< Activates speed of 106kbps. */
#define     JBIT_212KBPS            0x10   /*!< Activates speed of 212kbps. */
#define     JBIT_424KBPS            0x20   /*!< Activates speed of 424kbps. */

#define     JBIT_CRCEN              0x80   /*!< Activates transmit or receive CRC. */

/* TxControl Register						(14) */
#define     JBIT_INVTX2ON           0x80   /*!< Inverts the Tx2 output if drivers are switched on. */
#define     JBIT_INVTX1ON           0x40   /*!< Inverts the Tx1 output if drivers are switched on. */
#define     JBIT_INVTX2OFF          0x20   /*!< Inverts the Tx2 output if drivers are switched off. */
#define     JBIT_INVTX1OFF          0x10   /*!< Inverts the Tx1 output if drivers are switched off. */
#define     JBIT_TX2CW              0x08   /*!< Does not modulate the Tx2 output, only constant wave. */
#define     JBIT_TX2RFEN            0x02   /*!< Switches the driver for Tx2 pin on. */
#define     JBIT_TX1RFEN            0x01   /*!< Switches the driver for Tx1 pin on. */

/* Demod Register 							(19) */
#define     JBIT_FIXIQ              0x20   /*!< If set to 1 and the lower bit of AddIQ is set to 0, the receiving is fixed to I channel.
                                                If set to 1 and the lower bit of AddIQ is set to 1, the receiving is fixed to Q channel. */
/*@}*/


/*! \name RC522 Bit definitions of Page 2
 *  \ingroup reg
 *  Below there are useful bit definition of the RC522 register set.
 */
/*@{*/
/* TMode Register 							(2A) */
#define     JBIT_TAUTO              0x80   /*!< Sets the Timer start/stop conditions to Auto mode. */
#define     JBIT_TAUTORESTART       0x10   /*!< Restarts the timer automatically after finished
                                                counting down to 0. */
/*@}*/


/* /////////////////////////////////////////////////////////////////////////////
 * Bitmask Definitions
 * ////////////////////////////////////////////////////////////////////////// */
/*! \name RC522 Bitmask definitions
 *  \ingroup reg
 *  Below there are some useful mask defintions for the RC522. All specified
 *  bits are set to 1.
 */
/*@{*/

/* Command register                 (0x01)*/
#define     JMASK_COMMAND           0x0F   /*!< Bitmask for Command bits in Register JREG_COMMAND. */

/* Waterlevel register              (0x0B)*/
#define     JMASK_WATERLEVEL        0x3F   /*!< Bitmask for Waterlevel bits in register JREG_WATERLEVEL. */

/* Control register                 (0x0C)*/
#define     JMASK_RXBITS            0x07   /*!< Bitmask for RxLast bits in register JREG_CONTROL. */

/* Mode register                    (0x11)*/
#define     JMASK_CRCPRESET         0x03   /*!< Bitmask for CRCPreset bits in register JREG_MODE. */

/* TxMode register                  (0x12, 0x13)*/
#define     JMASK_SPEED             0x70   /*!< Bitmask for Tx/RxSpeed bits in register JREG_TXMODE and JREG_RXMODE. */

/* TxSel register                   (0x16)*/
#define     JMASK_DRIVERSEL         0x30   /*!< Bitmask for DriverSel bits in register JREG_TXSEL. */
#define     JMASK_SIGOUTSEL         0x0F   /*!< Bitmask for SigoutSel bits in register JREG_TXSEL. */

/* RxSel register                   (0x17)*/
#define     JMASK_UARTSEL           0xC0   /*!< Bitmask for UartSel bits in register JREG_RXSEL. */
#define     JMASK_RXWAIT            0x3F   /*!< Bitmask for RxWait bits in register JREG_RXSEL. */

/* RxThreshold register             (0x18)*/
#define     JMASK_MINLEVEL          0xF0   /*!< Bitmask for MinLevel bits in register JREG_RXTHRESHOLD. */
#define     JMASK_COLLEVEL          0x07   /*!< Bitmask for CollLevel bits in register JREG_RXTHRESHOLD. */

/* Demod register                   (0x19)*/
#define     JMASK_ADDIQ             0xC0   /*!< Bitmask for ADDIQ bits in register JREG_DEMOD. */
#define     JMASK_TAURCV            0x0C   /*!< Bitmask for TauRcv bits in register JREG_DEMOD. */
#define     JMASK_TAUSYNC           0x03   /*!< Bitmask for TauSync bits in register JREG_DEMOD. */

/* RFCfg register                   (0x26)*/
#define     JMASK_RXGAIN            0x70   /*!< Bitmask for RxGain bits in register JREG_RFCFG. */

/* GsN register                     (0x27)*/
#define     JMASK_CWGSN             0xF0   /*!< Bitmask for CWGsN bits in register JREG_GSN. */
#define     JMASK_MODGSN            0x0F   /*!< Bitmask for ModGsN bits in register JREG_GSN. */

/* CWGsP register                   (0x28)*/
#define     JMASK_CWGSP             0x3F   /*!< Bitmask for CWGsP bits in register JREG_CWGSP. */

/* ModGsP register                  (0x29)*/
#define     JMASK_MODGSP            0x3F   /*!< Bitmask for ModGsP bits in register JREG_MODGSP. */

/* TMode register                   (0x2A)*/
#define     JMASK_TGATED            0x60   /*!< Bitmask for TGated bits in register JREG_TMODE. */
#define     JMASK_TPRESCALER_HI     0x0F   /*!< Bitmask for TPrescalerHi bits in register JREG_TMODE. */

/*@}*/

#endif /* __RC522REG_H__ */

/* ///////////////////////////////////////////////////////////////////////////
 * End of File
 * //////////////////////////////////////////////////////////////////////// */