📄 rc522reg.h
字号:
/* /////////////////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) Philips Semiconductors
//
// All rights are reserved. Reproduction in whole or in part is
// prohibited without the written consent of the copyright owner.
// Philips reserves the right to make changes without notice at any time.
// Philips makes no warranty, expressed, implied or statutory, including but
// not limited to any implied warranty of merchantability or fitness for any
// particular purpose, or that the use will not infringe any third party patent,
// copyright or trademark. Philips must not be liable for any loss or damage
// arising from its use.
///////////////////////////////////////////////////////////////////////////////////////////////// */
/*! \file Rc522Reg.h
*
* Project: Object Oriented Library Framework RC522 register definitions.
*
* Source: Rc522Reg.h
* $Author: mha $
* $Revision: 1.30.1.5 $
* $Date: Mon Oct 18 09:01:58 2004 $
*
* $Author: Bob Jiang $
* $Revision: 1.3 $
* $Date: Fri Jul 22 2005 $
* Comment:
* RC522 register and bit definitions.
*
* History:
* MHa: Generated 07. May 2003
*
*/
#ifndef __RC522REG_H__
#define __RC522REG_H__
/*! \name Register definitions of Page 0
* \ingroup reg
* Following all register defintions of the RC522 Page 0.
*/
/*@{*/
#define JREG_RFU00 0x00 /* Currently not used. */
#define JREG_COMMAND 0x01 /*!< Contains Command bits, PowerDown bit and bit to
switch receiver off. */
#define JREG_COMMIEN 0x02 /*!< Contains Communication interrupt enable bits and
bit for Interrupt inversion. */
#define JREG_DIVIEN 0x03 /*!< Contains RfOn, RfOff, CRC and Mode Interrupt enable
and bit to switch Interrupt pin to PushPull mode. */
#define JREG_COMMIRQ 0x04 /*!< Contains Communication interrupt request bits. */
#define JREG_DIVIRQ 0x05 /*!< Contains RfOn, RfOff, CRC and Mode Interrupt request. */
#define JREG_ERROR 0x06 /*!< Contains Protocol, Parity, CRC, Collision, Buffer
overflow, Temperature and RF error flags. */
#define JREG_STATUS1 0x07 /*!< Contains status information about Lo- and HiAlert,
RF-field on, Timer, Interrupt request and CRC status. */
#define JREG_STATUS2 0x08 /*!< Contains information about internal states (Modemstate),
Mifare states and possibility to switch Temperature
sensor off. */
#define JREG_FIFODATA 0x09 /*!< Gives access to FIFO. Writing to register increments the
FIFO level (register 0x0A), reading decrements it. */
#define JREG_FIFOLEVEL 0x0A /*!< Contains the actual level of the FIFO. */
#define JREG_WATERLEVEL 0x0B /*!< Contains the Waterlevel value for the FIFO */
#define JREG_CONTROL 0x0C /*!< Contains information about last received bits and to
Start and stop the Timer unit. */
#define JREG_BITFRAMING 0x0D /*!< Contains information of last bits to send, to align
received bits in FIFO and activate sending in Transceive*/
#define JREG_COLL 0x0E /*!< Contains all necessary bits for Collission handling */
#define JREG_RFU0F 0x0F /* Currently not used. */
/*@}*/
/*! \name Register definitions of Page 1
* \ingroup reg
* Following all register defintions of the RC522 Page 1.
*/
/*@{*/
#define JREG_RFU10 0x10 /* Currently not used. */
#define JREG_MODE 0x11 /*!< Contains bits for auto wait on Rf, to detect SYNC byte in
NFC mode and MSB first for CRC calculation */
#define JREG_TXMODE 0x12 /*!< Contains Transmit Framing, Speed, CRC enable, bit for
inverse mode and TXMix bit. */
#define JREG_RXMODE 0x13 /*!< Contains Transmit Framing, Speed, CRC enable, bit for
multiple receive and to filter errors. */
#define JREG_TXCONTROL 0x14 /*!< Contains bits to activate and configure Tx1 and Tx2 and
bit to activate 100% modulation. */
#define JREG_TXAUTO 0x15 /* */
#define JREG_TXSEL 0x16 /*!< Contains SigoutSel, DriverSel and LoadModSel bits. */
#define JREG_RXSEL 0x17 /*!< Contains UartSel and RxWait bits. */
#define JREG_RXTRESHOLD 0x18 /*!< Contains MinLevel and CollLevel for detection. */
#define JREG_DEMOD 0x19 /*!< Contains bits for time constants, hysteresis and
IQ demodulator settings. */
#define JREG_RFU1A 0x1A /* */
#define JREG_RFU1B 0x1B /* */
#define JREG_MIFNFC 0x1C /* */
#define JREG_RFU1D 0x1D /* */
#define JREG_RFU1E 0x1E /* Currently not used. */
#define JREG_SERIALSPEED 0x1F /*!< Contains speed settings for serila interface. */
/*@}*/
/*! \name Register definitions of Page 2
* \ingroup reg
* Following all register defintions of the RC522 Page 2.
*/
/*@{*/
#define JREG_RFU20 0x20 /* Currently not used. */
#define JREG_CRCRESULT1 0x21 /*!< Contains MSByte of CRC Result. */
#define JREG_CRCRESULT2 0x22 /*!< Contains LSByte of CRC Result. */
#define JREG_GSNOFF 0x23 /* Currently not used. */
#define JREG_MODWIDTH 0x24 /*!< Contains modulation width setting. */
#define JREG_TXBITPHASE 0x25 /* Currently not used. */
#define JREG_RFCFG 0x26 /*!< Contains sensitivity of Rf Level detector, the receiver
gain factor and the RfLevelAmp. */
#define JREG_GSN 0x27 /*!< Contains the conductance and the modulation settings for
the N-MOS transistor. */
#define JREG_CWGSP 0x28 /*!< Contains the conductance for the P-Mos transistor. */
#define JREG_MODGSP 0x29 /*!< Contains the modulation index for the PMos transistor. */
#define JREG_TMODE 0x2A /*!< Contains all settings for the timer and the highest 4
bits of the prescaler. */
#define JREG_TPRESCALER 0x2B /*!< Contais the lowest byte of the prescaler. */
#define JREG_TRELOADHI 0x2C /*!< Contains the high byte of the reload value. */
#define JREG_TRELOADLO 0x2D /*!< Contains the low byte of the reload value. */
#define JREG_TCOUNTERVALHI 0x2E /*!< Contains the high byte of the counter value. */
#define JREG_TCOUNTERVALLO 0x2F /*!< Contains the low byte of the counter value. */
/*@}*/
/*! \name Register definitions of Page 3
* \ingroup reg
* Following all register defintions of the RC522 Page 3.
*/
/*@{*/
#define JREG_RFU30 0x30 /* Currently not used. */
#define JREG_TESTSEL1 0x31 /* Test register */
#define JREG_TESTSEL2 0x32 /* Test register */
#define JREG_TESTPINEN 0x33 /* Test register */
#define JREG_TESTPINVALUE 0x34 /* Test register */
#define JREG_TESTBUS 0x35 /* Test register */
#define JREG_AUTOTEST 0x36 /* Test register */
#define JREG_VERSION 0x37 /*!< Contains the product number and the version. */
#define JREG_ANALOGTEST 0x38 /* Test register */
#define JREG_TESTDAC1 0x39 /* Test register */
#define JREG_TESTDAC2 0x3A /* Test register */
#define JREG_TESTADC 0x3B /* Test register */
#define JREG_ANALOGUETEST1 0x3C /* Test register */
#define JREG_RFT3D 0x3D /* Test register */
#define JREG_RFT3E 0x3E /* Test register */
#define JREG_RFT3F 0x3F /* Test register */
/*@}*/
/* /////////////////////////////////////////////////////////////////////////////
* Possible commands
* ////////////////////////////////////////////////////////////////////////// */
/*! \name RC522 Command definitions
* \ingroup reg
* Following all commands of the RC522.
*/
/*@{*/
#define JCMD_IDLE 0x00 /*!< No action: cancel current command
or home state. \n */
#define JCMD_CONFIG 0x01
#define JCMD_GENRANDOM 0x02
#define JCMD_CALCCRC 0x03 /*!< Activate the CRC-Coprocessor \n<em><strong>
Remark: </strong>The result of the CRC calculation can
be read from the register CRCResultXXX </em>*/
#define JCMD_TRANSMIT 0x04 /*!< Transmit data from FIFO to the card \n<em>
<strong>Remark: </strong>If data is already in
the FIFO when the command is activated, this data is
transmitted immediately. It is possible to
write data to the FIFO while the Transmit
command is active. Thus it is possible to
transmit an unlimited number of bytes in one
stream by writting them to the FIFO in time.</em>*/
#define JCMD_NOCMDCHANGE 0x07 /*!< This command does not change the actual commant of
the RC522 and can only be written. \n<em><strong>
Remark: </strong>This command is used for WakeUp procedure
of RC522 to not change the current state. </em>*/
#define JCMD_RECEIVE 0x08 /*!< Activate Receiver Circuitry. Before the
receiver actually starts, the state machine
waits until the time configured in the
register RxWait has passed. \n<em><strong>
Remark: </strong>It is possible to read any received
data from the FIFO while the Receive command
is active. Thus it is possible to receive an
unlimited number of bytes by reading them
from the FIFO in time. </em>*/
#define JCMD_TRANSCEIVE 0x0C /*!< This Command has two modes:\n
Transmits data from FIFO to the card and after
that automatically activates
the receiver. Before the receiver actually
starts,the state machine waits until the
time configured in the register RxWait has
passed. \n <em><strong>
Remark: </strong>This command is the combination of
Transmit and Receive.</em> */
#define JCMD_AUTOCOLL 0x0d
#define JCMD_AUTHENT 0x0E /*!< Perform the card authentication using the
Crypto1 algorithm.
\n <em><strong>Remark: </strong></em>*/
#define JCMD_SOFTRESET 0x0F /*!< Runs the Reset- and Initialisation Phase
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -