📄 rtxconf.lst
字号:
363 ;* EXPORTS
364 ;*----------------------------------------------------------------------*
365
366 ; System constants
367 PUBLIC ?RTX_EXTRENTSIZE, ?RTX_EXTSTKSIZE, ?RTX_INTSTKSIZE
368 PUBLIC ?RTX_TIMESHARING, ?RTX_BANKSWITCHING, ?RTX_INTREGSIZE
369 PUBLIC ?RTX_MAILBOX_SUPPORT, ?RTX_SEMAPHORE_SUPPORT
370
371 ; Initial Interrupt mask values
372 PUBLIC ?RTX_IE_INIT, ?RTX_IEN1_INIT, ?RTX_IEN2_INIT
373
374 ; Enable the interrupt enable registers for the selected processor
375 PUBLIC ?RTX_INIT_INT_REG_FLAGS
376
377 ; Interrupt number to enable-mask table
378 PUBLIC ?RTX_INT_TO_BIT_TABLE_BASE
379
380 ; Greatest interrupt number
381 PUBLIC ?RTX_MAX_INT_NBR
382
383 ; Processor specific interrupt enable masks
384 PUBLIC ?RTX_IE, ?RTX_IEN1, ?RTX_IEN2
385
386 ; Interrupt mask variables
387 PUBLIC ?RTX_NM_IE, ?RTX_D_IE, ?RTX_ND_IE
388 PUBLIC ?RTX_NM_IE1, ?RTX_D_IE1, ?RTX_ND_IE1
389 PUBLIC ?RTX_NM_IE2, ?RTX_D_IE2, ?RTX_ND_IE2
390
391 ; System Timer constants
392 PUBLIC ?RTX_CLK_INT_NBR ; EQUATE
393 PUBLIC ?RTX_TLOW, ?RTX_THIGH, ?RTX_TMOD ; DATA
394 PUBLIC ?RTX_TCON ; DATA
395 PUBLIC ?RTX_TFLAG, ?RTX_TCONTROL ; BIT
396 PUBLIC ?RTX_TMOD_AND_MASK, ?RTX_TMOD_OR_MASK ; EQUATES
397 PUBLIC ?RTX_TCON_AND_MASK, ?RTX_TCON_OR_MASK ; EQUATES
398
399 ; Bank-Switching Support
400 PUBLIC ?RTX_SWITCHBANK ; CODE
401 PUBLIC ?RTX_SAVE_INT_BANK ; DATA
402 IF (?RTX_BANKSWITCHING = 0)
403 PUBLIC ?B_CURRENTBANK ; Dummy DATA-Definition
404 ENDIF
405
406 ; Idle function
407 PUBLIC ?RTX_IDLE_FUNC
408
409 ; Mailbox and semaphore FIFO space
410 PUBLIC ?RTX_MBX_PAGE
411 PUBLIC ?RTX_MBX_PAGE_END
412 PUBLIC ?RTX_SEM_PAGE
413 PUBLIC ?RTX_SEM_PAGE_END
414
415
416 ;*----------------------------------------------------------------------*
417 ;* MACROS
418 ;*----------------------------------------------------------------------*
419
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 10/09/2000 13:18:25 PAGE 7
420 ; This MACRO generates an RTX-51 interrupt entry point using the base
421 ; address ?RTX_INTBASE.
422
423 INT_ENTRY MACRO NO
424 EXTRN XDATA (?RTX_INT&NO&_TID)
425 PUBLIC INT&NO&_VECTOR
426 CSEG AT(?RTX_INTBASE+3+(&NO&*8))
427 INT&NO&_VECTOR: MOV ?RTX_TMP1, A ; Save A
428 MOV A, #LOW(?RTX_INT&NO&_TID); Set up ptr to int. TID
429 LJMP ?RTX_INT_HANDLER ; Jump to general ISR
430 ENDM
431
432
433 ;*----------------------------------------------------------------------*
434 ;* PROCESSOR SPECIFIC DATA DEFINITIONS
435 ;*----------------------------------------------------------------------*
436
ELSEIF (?RTX_CPU_TYPE = 2)
506 ;**********
507 ;* Type 2 *
508 ;**********
509 ;------------------------------------------------------------------
510 ; Define the number and addresses of the interrupt enable registers
511 ; 8052 -> 1 interrupt enable register
512 ; (Set the not used registers to the same address as ?RTX_IE)
513
0001 514 INT_EN_MASK_NUMBER EQU 1
00A8 515 ?RTX_IE DATA 0A8H
00A8 516 ?RTX_IEN1 DATA 0A8H ; not used
00A8 517 ?RTX_IEN2 DATA 0A8H ; not used
518
519 ;------------------------------------------------------------------
520 ; Generate the interrupt entry points supported by the peripherals
521 ; of the selected CPU type.
522 IF (?RTX_SYSTEM_TIMER = 0)
523 ; Do NOT include the Timer 0 Vector (INT-1)
ENDIF
574
575 ;------------------------------------------------------------------
576 ; The following table attaches the interrupt numbers (0..31) to the
577 ; corresponding bits in the interrupt enable masks of the specific
578 ; processor.
579 ; All three interrupt enable register contents must be defined
580 ; for every interrupt number (even when the specific processor contains
581 ; only one interrupt mask).
582 ; Syntax: DB IE-content, IE1-content, IE2-content
583 ;
584 ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF SEGMENT CODE
---- 585 RSEG ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF
586
0000 587 ?RTX_INT_TO_BIT_TABLE_BASE:
0000 010000 588 DB 01H, 00H, 00H ; INT_0 (P3.2/INT0)
0003 020000 589 DB 02H, 00H, 00H ; INT_1 (Timer 0)
0006 040000 590 DB 04H, 00H, 00H ; INT_2 (P3.3/INT1)
0009 080000 591 DB 08H, 00H, 00H ; INT_3 (Timer 1)
000C 100000 592 DB 10H, 00H, 00H ; INT_4 (Ser. channel)
000F 200000 593 DB 20H, 00H, 00H ; INT_5 (Timer 2)
594
595 ;------------------------------------------------------------------
596 ; Define the greatest supported interrupt number
0005 597 ?RTX_MAX_INT_NBR EQU 5
598
0087 599 PCON DATA 87H
600
601 ENTER_IDLE MACRO
602 ;;
603 ;; Enter Idle Mode
604 ;; ---------------
605 ;; Not supported by all 8052 type processors (see manufacturer's
606 ;; data sheet !)
607 ;; To be used whenever entering idle state.
608 ;;
609 ORL PCON, #01H ; Set idle mode (leave by interrupt)
610 ; (peripherals stay active)
611 ENDM
612
$endif
2359
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 10/09/2000 13:18:25 PAGE 8
2360
2361
2362 $eject
A51 MACRO ASSEMBLER RTX-51 CONFIGURATION 10/09/2000 13:18:25 PAGE 9
2363 ;*----------------------------------------------------------------------*
2364 ;* DEFINITIONS COMMON FOR ALL PROCESSORS
2365 ;*----------------------------------------------------------------------*
2366
2367 ;------------------------------------------------------------------
2368 ; Define the internal interrupt mask variables. The variables are
2369 ; used for the Interrupt-Handling.
2370 ; Initialise the enable bits for the Interrupt-Enable-Masks
2371 ;
2372 IF (INT_EN_MASK_NUMBER = 1)
2373 ?RTX?INT_MASK?RTXCONF SEGMENT DATA
---- 2374 RSEG ?RTX?INT_MASK?RTXCONF
2375 ; variables for first mask
0000 2376 ?RTX_NM_IE: DS 1
0001 2377 ?RTX_D_IE: DS 1
0002 2378 ?RTX_ND_IE: DS 1
2379 ; variables for second mask (not used)
0003 2380 ?RTX_NM_IE1: DS 0
0003 2381 ?RTX_D_IE1: DS 0
0003 2382 ?RTX_ND_IE1: DS 0
2383 ; variables for third mask (not used)
0003 2384 ?RTX_NM_IE2: DS 0
0003 2385 ?RTX_D_IE2: DS 0
0003 2386 ?RTX_ND_IE2: DS 0
2387
2388 ; RTX-51 calls this routine in the initialisation phase
2389 ?RTX?RTX_INIT_INT_REG_FLAGS?RTXCONF SEGMENT CODE
---- 2390 RSEG ?RTX?RTX_INIT_INT_REG_FLAGS?RTXCONF
0000 2391 ?RTX_INIT_INT_REG_FLAGS:
0000 C200 F 2392 CLR ?RTX_ENA_INT_REG1
0002 C200 F 2393 CLR ?RTX_ENA_INT_REG2
0004 22 2394 RET
ENDIF
2442
2443
2444 ;------------------------------------------------------------------
2445 ; Define the System-Timer specific values
2446 ; This values are normally for all 8051 family-members identical.
2447 ;
2448 IF (?RTX_SYSTEM_TIMER = 0)
008A 2449 ?RTX_TLOW DATA 8AH
008C 2450 ?RTX_THIGH DATA 8CH
0088 2451 ?RTX_TCON DATA 88H
0089 2452 ?RTX_TMOD DATA 89H
008D 2453 ?RTX_TFLAG BIT 8DH
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -