changedl.vhd

步进电机8细分CPLD相序及外部DA输出 实际细分数可达64细分 使用Atmel maxplus2 V10.1软件

library IEEE;
use IEEE.std_logic_1164.all;


entity changedl is
    port (

          ADDR:  in STD_LOGIC_VECTOR (3 downto 0);
          DAT :  out STD_LOGIC_VECTOR (11 downto 0)
    );
end changedl;

architecture behave of changedl is
 
begin
  -- <<enter your statements here>>
  process(ADDR )
 -- variable DAT_temp  :STD_LOGIC_VECTOR (11 downto 0) ;
    begin 

		case ADDR is
			when "0000" => DAT<="000000111111" ;--1
			when "0001" => DAT<="001100111110" ;--2
			when "0010" => DAT<="011000111010" ;--3
			when "0011" => DAT<="100011110100" ;--4
			when "0100" => DAT<="101101101101" ;--5
			when "0101" => DAT<="110100100011" ;--6
			when "0110" => DAT<="111010011000" ;--7
			when "0111" => DAT<="111110001100" ;--8
			when "1000" => DAT<="111111000000" ;--9-----------
			when "1001" => DAT<="111110001100" ;--10
			when "1010" => DAT<="111010011000" ;--11
 			when "1011" => DAT<="110100100011" ;--12
			when "1100" => DAT<="101101101101" ;--13
			when "1101" => DAT<="100011110100" ;--14
			when "1110" => DAT<="011000111010" ;--15
			when "1111" => DAT<="001100111110" ;--16
			when others => DAT<="000000000000" ;
	   end case;

    end process; 
 end behave;