cout40.vhd

步进电机8细分CPLD相序及外部DA输出 实际细分数可达64细分 使用Atmel maxplus2 V10.1软件

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity cout40 is
    port (
        SEL:   in STD_LOGIC_VECTOR (2 downto 0);
        CLK:   in STD_LOGIC;
        DIRCH: in std_logic;
		AD   : out STD_LOGIC_VECTOR (2 downto 0);
        ADDRESS: out STD_LOGIC_VECTOR (3 downto 0)
    );
end cout40;

architecture behave of cout40 is
begin
  -- <<enter your statements here>>    
    process(CLK)
    variable addr_temp     :STD_LOGIC_VECTOR (3 downto 0) ; 
	variable add_temp      :STD_LOGIC_VECTOR (2 downto 0) ; 
    variable port_sel_val  :INTEGER range 0 to 4;     
    variable dirchtemp     :STD_LOGIC;
    begin  
 	 if CLK'event and CLK='1' then
             
        case SEL is
                when "000" => port_sel_val:=1; 
                when "001" => port_sel_val:=1;  
                when "010" => port_sel_val:=1;  
                when others =>port_sel_val:=1;  
         end case;     
                      
        If DIRCH='1' then           --forword                          
               addr_temp:=addr_temp+port_sel_val  ;
			   if addr_temp=0 or addr_temp=1 or addr_temp=8 or addr_temp=9  then
			      add_temp:=add_temp+port_sel_val ; 
                                                      
          	   end if;
           
              

        else                      --backword                            
              addr_temp:=addr_temp-port_sel_val  ;
			 
                if addr_temp=0 or addr_temp=7  or addr_temp=8 or addr_temp=15 then
			       add_temp:=add_temp-port_sel_val ;                                                     
          	   end if;
			 
        end if;
     AD<=  add_temp ;
    ADDRESS<=addr_temp ;
	 	 
  end if;	 
  end process;       
end behave;